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The present work demonstrates, for the first time, the impact of back-end-of-line (BEOL) design on the electrical reliability of SiGe heterojunction bipolar transistors (HBTs). Mixed-mode and high-current stress were performed for four different SiGe HBT variants designed with varying levels of dummy metal over-layers. The avalanche multiplication factor was found to be insensitive to changes in the BEOL, and thus the classical mixed-mode degradation was found to be similar across all BEOL variants. Meanwhile, high-current stress showed that adding more dummy metal layers alleviated the current gain and base current density degradation by 30% and 100%, respectively. Both the mechanical stress and temperature differences due to additional dummy metal layers were investigated using calibrated technology computer-aided design (TCAD) simulations. To assess RF implications, small-signal transition frequency ( ${f}_{T}$ ) improved by about 21%, and large-signal power added efficiency (PAE) increased by about 4% while the RF breakdown remained unchanged. The present study sheds light on the impact of reliability on dummy BEOL design, as well as its potential performance enhancement for circuit design in a manner that incurs no additional concern for electrical reliability under nominal conditions.

The present work investigates the impact of transistor layout on both the RF and thermal performance of 90-nm SiGe heterojunction bipolar transistors (HBTs). The resulting performance shows only slight degradation in small-signal RF figures-of-merit, while large-signal RF figures-of-merit relevant to power amplifiers (PAs) are improved. Thermal resistance and capacitance were extracted for five different SiGe HBT layouts with the same total emitter area. Additionally, a favorable trade-off exists between RF performance figures-of-merit and thermal parameters; namely, the thermal time constant can be reduced by up to 37% with optimal layout, with only slight degradation (up to 8%) in RF performance. These optimal device layout variations can help circuit designers mitigate thermal memory effects at the device level, thereby improving the overall large-signal linearity of PAs.