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Wireless communication infrastructure is a key enabling technology for smart cities. This paper investigates a novel technique to enhance the performance of 5G base stations by addressing the compensation of nonlinear distortions caused by radiofrequency power amplifiers. For this purpose, a sequential digital predistortion approach that uses twin nonlinear two-box structure along with reduced sampling rates in the feedback path is proposed to implement a linearization system. Such a system is shown to have a correction bandwidth that exceeds the bandwidth of the feedback path. This is achieved by synthesizing the predistortion function in two successive characterization iterations. Both characterizations use the same hardware, which has a reduced sampling rate in the feedback path. Hence, the proposed predistorter scheme does not require any additional hardware compared to standard schemes. Moreover, coarse delay alignment is performed while identifying the memory polynomial function in order to further reduce the computational complexity of the proposed system. Experimental results using an inverse Class-F power amplifier demonstrate the ability of the proposed predistorter to achieve a correction bandwidth of 100 MHz with a feedback sampling rate as low as 25 MSa/s.

The feasibility of implementing digital predistortion for next-generation wireless communication is faced with a dilemma due to the ever-increasing demand for faster data rates. This causes the utilized bandwidth to increase significantly, as seen in the 5G NR standard in which bandwidths as high as 400 MHz are utilized. Hence, the development of new predistortion techniques in which the forward and feedback paths operate at lower sampling rates is of utmost importance to realize efficient and practical predistortion solutions. In this work, a novel predistortion technique is presented by which the predistortion is divided between the digital and analog domains. The predistorter is composed of a memoryless AM/AM gain function that is implementable in the analog domain, and a nonlinear model with memory effects in the digital domain to relax the sampling rate requirements on both the forward and feedback paths. Experimental validation was carried out with a 20 MHz and a 40 MHz 5G signal, and the results indicate minimal linearization degradation with a sampling rate reduction of 50% and 30%, respectively. This sampling rate reduction is concurrently applied in the digital-to-analog converter of the forward path and the analog-to-digital converter of the feedback path.