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VCO-based ADCs widely utilize coarse-fine readout to save power and hardware compared to counter-only converters. However, the timing mismatch due to the clock skew between the coarse and fine quantizers can lead to significant reconstruction errors. This brief proposes a digital calibration circuit to detect and correct coarse-fine timing mismatch for VCO-based ADCs. The circuit includes overcount/undercount logic to detect all possible timing mismatch cases and generates a correction value to digitally remove the errors. The calibration operates continuously in the background and is entirely digital, making it scaling-friendly and robust against analog imperfections. Simulations show that a VCO-based ADC utilizing the calibration circuit improves the SNR by 10.3 dB and 6.9 dB versus a conventional coarse-fine converter and one with a conventional retiming calibration, respectively.

Trade-offs in the design of wideband and energy-efficient inverter-based amplifiers (IAs) will be analyzed and compared to the conventional Current-Mode Logic (CML) based circuits. For a proper comparison, the minimum current consumption of generic IA and the CML amplifiers, with and without active-peaking, will be calculated for a set of target Gain-Bandwidth Product (GBWP) values. This study shows that IAs consume not only lower energy and power compared to their CML counterparts for a given speed specification, but also offer a higher maximum achievable operating frequency. Closed-form expressions, with less than 5% mismatch with simulation results, will be provided to analyze speed-power trade-offs in this type of circuit. This study shows that the consumption of IA circuits (with active peaking) can be lowered by a factor of close to two compared to the CML (with active peaking) in CMOS 28 nm technology, while extending the maximum achievable GBWP by about 12%.

This brief presents an analytical approach, supported by experimental data, to design analog circuits for given noise and speed specifications. As an extension to traditional design methodologies, i.e., Inversion Coefficient (IC) and $\mathrm { g_{m}/I_{D} }$ (GmID), the proposed approach aims to gain more in-depth insight, while providing appropriate analytical means for circuit design, at lower levels of computing complexity. Based on a recently proposed design approach, the $\mathrm { C/I_{D} }$ method relies on device characteristic capacitance, i.e., $\mathscr {C}_{S} = \mathrm { C_{S}/I_{D} }$ as an invariant, where $\mathrm {C_{S}}$ refers to the Field-Effect Transistor (FET) device self-loading capacitance. $\mathrm { C/I_{D} }$ provides the opportunity to derive closed-form solutions to some key design optimization problems such as power versus Gain Bandwidth (GBW) and noise trade-offs. Examples for common-source amplifiers and Ring Oscillators (RO) have been provided. A set of current-steering ROs has been designed and fabricated in $0.18~\mathrm {\mu }\text{m}$ technology based on the proposed flow. The circuit Phase Noise (PN) was characterized and compared to the predictions of the proposed design methodology, demonstrating favorable matching.