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Humans rely increasingly on sensors to address grand challenges and to improve quality of life in the era of digitalization and big data. For ubiquitous sensing, flexible sensors are developed to overcome the limitations of conventional rigid counterparts. Despite rapid advancement in bench-side research over the last decade, the market adoption of flexible sensors remains limited. To ease and to expedite their deployment, here, we identify bottlenecks hindering the maturation of flexible sensors and propose promising solutions. We first analyze challenges in achieving satisfactory sensing performance for real-world applications and then summarize issues in compatible sensor-biology interfaces, followed by brief discussions on powering and connecting sensor networks. Issues en route to commercialization and for sustainable growth of the sector are also analyzed, highlighting environmental concerns and emphasizing nontechnical issues such as business, regulatory, and ethical considerations. Additionally, we look at future intelligent flexible sensors. In proposing a comprehensive roadmap, we hope to steer research efforts towards common goals and to guide coordinated development strategies from disparate communities. Through such collaborative efforts, scientific breakthroughs can be made sooner and capitalized for the betterment of humanity.

The thermal conductivity measurement of films with submicrometer thicknesses is difficult due to their exceptionally low thermal resistance, which makes it challenging to accurately measure the temperature changes that occur as heat flows through the film. Thus, specialized and sensitive measurement techniques are required. 3ω method is a widely used and reliable tool for measuring the thermal conductivity of films. However, the high in-plane thermal conductivity in thin films results in rapid heat dissipation across the thin film, resulting in poor measurement sensitivity and making it difficult to accurately measure the temperature gradient with the traditional 3ω method. Also, the traditional 3ω method requires cross-plane thermal conductivity to derive the in-plane counterpart. Here, we introduce a dual-domain 3ω method that adopts AC-modulated heating and electrode arrays facilitating surface temperature profiling: (1) the sensitivity was significantly improved due to the employment of low-thermal-conductivity-substrate, and (2) cross-plane thermal conductivity is not required for the analysis of in-plane counterpart. This measurement platform allows us to control heat penetration in depth via varied heating frequencies as well as spatial temperature detection through laterally distributed electrodes on the thin film surface. By utilizing the described method, we have determined the in-plane thermal conductivity of a copper film, having a thickness of 300 nm, which was found to be 346 Wm−1K−1 and validated by the Wiedemann–Franz law. [ABSTRACT FROM AUTHOR]

Analog resistive random access memory (RRAM) devices enable parallelized nonvolatile in-memory vector-matrix multiplications for neural networks eliminating the bottlenecks posed by von Neumann architecture. While using RRAMs improves the accelerator performance and enables their deployment at the edge, the high tuning time needed to update the RRAM conductance states adds significant burden and latency to real-time system training. In this article, we develop an in-memory discrete Fourier transform (DFT)-based convolution methodology to reduce system latency and input regeneration. By storing the static DFT/inverse DFT (IDFT) coefficients within the analog arrays, we keep digital computational operations using digital circuits to a minimum. By performing the convolution in reciprocal Fourier space, our approach minimizes connection weight updates, which significantly accelerates both neural network training and interference. Moreover, by minimizing RRAM conductance update frequency, we mitigate the endurance limitations of resistive nonvolatile memories. We show that by leveraging the symmetry and linearity of DFT/IDFTs, we can reduce the power by 1.57 × for convolution over conventional execution. The designed hardware-aware deep neural network (DNN) inference accelerator enhances the peak power efficiency by 28.02 × and area efficiency by 8.7 × over state-of-the-art accelerators. This article paves the way for ultrafast, low-power, compact hardware accelerators.