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Evidence of microscopic inhomogeneities of the side source/drain contacts in 300 mm wafer integrated MoS2 field-effect transistors is presented. In particular, the presence of a limited number of low Schottky barrier spots through which channel carriers are predominantly injected is demonstrated by the dramatic current changes induced by individual charge traps located near the source contact. Two distinct types of "contact-impacting traps" are identified. Type-1 trap is adjacent to the contact interface and exchanges carriers with the metal. Its impact is only observable when the adjacent contact is the reverse-biased FET source and limits the channel current. Type-2 trap is located in the AlOx gate oxide interlayer, near the source contact, and exchanges carriers with the channel. Its capture/emission time constants exhibit both a gate and drain bias dependence due to the high sensitivity of the contact regions to the applied lateral and vertical fields. Unlike typical channel-impacting oxide traps, both types of reported defects affect the Schottky barrier height and width rather than the threshold voltage and result in giant random telegraph noise (RTN). These observations indicate that the contact quality and geometry play a fundamental role in the ultimate scaling of 2D FETs. [ABSTRACT FROM AUTHOR]

Field‐effect transistors (FETs), using transition metal dichalcogenides (TMD) as channels, have various types of interfaces, and their characteristics are sensitively changed in temperature and electrical stress. In this article, the effect of fast cyclic thermal stress on the performance of FETs using TMD as a channel is investigated and introduced. The Al2O3 passivation layer is deposited onto the TMD channel by atomic layer deposition process, and the hysteresis decreases and the direction changes from clockwise to counterclockwise. Applying cyclic thermal stress that rapidly heats and cools by 90 K in a 20 s cycle increases and decreases drain current repeatedly as charges move between the TMD channel and the interface traps. As cyclic thermal stress is applied, permanent interfacial damage occurs, resulting in increased interface trap density at the bottom and decreased hysteresis. These experimental results are also shown through technology computer‐aided design simulations. In addition, series resistance and mobility attenuation factor increase due to the concentration of the conduction paths at the bottom of the channel. [ABSTRACT FROM AUTHOR]