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Titanium Silicide (TiSi2 is a primary contact material with low-resistance contact characteristics used in nanodevices. However, the rapid scaling trend requires further improvement to achieve both high thermal stability and low contact resistivity. Herein, a method for simultaneously improving the contact resistivity and thermal stability of the TiSi2 /Si interface is proposed by inserting a Ta interlayer into Ti/p-Si. The Ta-interlayered TiSi2 (Ta IL TiSi2) achieves an improved contact resistivity by approximately 7.9 times compared to that without the Ta interlayer. This remarkable improvement is due to the smooth contact morphology resulting from the suppressed excess diffusion of Ti and Si and dopant segregation at the TiSi2/Si interface. Particularly, because additional reaction during post annealing is minimized by the Ta interlayer, Ta IL TiSi2 shows a low sheet resistance of $3.71~\Omega /\Box $ even after post annealing at 600 °C & 30 min, which is much lower than the conventional TiSi2 scheme under the same annealing conditions. These results are expected to provide insights into state-of-the-art CMOS-based devices that require both low contact resistivity and better thermal margins.

With the significant technological developments in recent times, the neuromorphic system has been receiving considerable attention owing to its parallel arithmetic, low power consumption, and high scalability. However, the low reliability of artificial synapse devices disturbs calculations and causes inaccurate results in neuromorphic systems. In this paper, we propose a stable resistive artificial synapse (RAS) device with nitrogen-doped titanium oxide (TiOx:N)-based resistive switching (RS) memory. The TiOx:N-based RAS, compared to the TiOx-based RAS, demonstrates more stable RS characteristics in current–voltage (I–V) and pulse measurements. In terms of resistance variability, the TiOx:N-based RAS demonstrates five times lower resistance variability at 1.38%, compared to 6.68% with the TiOx-based RAS. In addition, we verified the relation between the neuromorphic system and the resistance reliability of the synapse device for the first time. The pattern recognition simulation is performed using an artificial neural network (ANN) consisting of artificial synapse devices using the Modified National Institute of Standards and Technology dataset. In the simulation, the ANN with the TiOx:N-based RAS exhibited significant pattern recognition accuracy of 64.41%, while the ANN with TiOx-based RAS demonstrated only low recognition accuracy of 22.07%. According to the results of subsequent simulations, the pattern recognition accuracy exponentially decreases when the resistance variability exceeds 5%. Therefore, for implementing a stable neuromorphic system, the synapse device in the neuromorphic system has to maintain low resistance variability. The proposed nitrogen-doped synapse device is suitable for neuromorphic systems because reliable resistance variability can be obtained with only simple process steps.

Optimizing the contact structure while reducing the contact resistance in advanced transistors has become an extremely challenging problem. Because the existing techniques are limited to controlling only one semiconductor type, either n- or p-type, owing to their work function differences, significant challenges are encountered in the integration of a contact structure and metal suitable for both n- and p-type semiconductors. This is a formidable drawback of the complementary metal-oxide-semiconductor (CMOS) technology. In this paper, we demonstrate the effectiveness of a metal/graphene/semiconductor (MGrS) as a universal source/drain contact structure for both n- and p-type transistors. The MGrS contact structure significantly enhanced the reverse current density (JR) and reduced the Schottky barrier height (SBH) for both semiconductor types. From the analysis of the SBH values and their relationship with the metal work function, which refers to the S-parameter, the van der Waals contact of graphene (Gr) effectively alleviated the Fermi level (FL) pinning for both semiconductor types, reducing the metal-induced gap states (MIGS) at the Gr/semiconductor interface. Furthermore, Gr effectively modulated the work function of the contact metal to yield a position favorable for each semiconductor type. Consequently, a single MGrS contact structure on a Si substrate resulted in excellent Ohmic contacts in both n- and p-type Si, with SBH values reduced to 0.012 and 0.024 eV for n- and p-type Si, respectively. This new approach for integrating the contact structures of semiconductor types will lead to extended capabilities for high-performance device applications and CMOS logical circuitry.