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In this work, a charge-based memristor emulator is designed using a single active current mode component Differential Voltage Current Conveyor Transconductance Amplifier with one capacitor and two resistors as passive components. Importantly, the proposed circuit topology can be changed to either grounded or floating configuration using a single switch. Moreover, the proposed memristor design can be operated either in incremental or decremental configuration by using another switch. Therefore, using only two switches, the same circuitry can be utilized to design the floating/grounded incremental/decremental memristor. The pinched hysteresis loop area can be controlled by applying different biasing voltages. Further, the mathematical analysis is performed to drive the theoretical TiO2 based results for the proposed memristor emulator. In addition, simulations confirming the theoretical analysis are conducted in PSPICE using the 180 nm TSMC technology with a supply voltage of ± 0.9 V by varying frequencies and capacitances to obtain a pinched hysteresis loop. The presented circuit performs effectively for frequencies upto 500 MHz while operating with grounded type memristor and 300 MHz with floating type design. To check the ability to remember the history of the proposed memristor, the non-volatility test is performed for both the incremental and decremental configurations. Moreover, the suggested memristor design is applied in an adaptive learning circuit to prove its feasibility in neuromorphic applications. [ABSTRACT FROM AUTHOR]

This paper presents a current-mode VCSEL driver (CMVD) implemented using 180 nm CMOS technology for application in short-range LiDAR sensors, in which current-steering logic is suggested to deliver modulation currents from 0.1 to 10 mApp and a bias current of 0.1 mA simultaneously to the VCSEL diode. For the simulations, the VCSEL diode is modeled with a 1.6 V forward-bias voltage and a 50 Ω series resistor. The post-layout simulations of the proposed CMVD clearly demonstrate large output pulses and eye-diagrams. Measurements of the CMVD demonstrate large output pulses, confirming the simulation results. The chip consumes a maximum of 11 mW from a 3.3 V supply, and the core occupies an area of 0.1 mm2. [ABSTRACT FROM AUTHOR]

The work examines the main technical indicators of electromechanical converters callers with levitation elements, a generalized design method has been developed tions, as well as design diagrams and functional dependencies of the main varieties of electromechanical devices with elements of levitation. Analytical expressions for the levitation coefficient as a function of the dimensions of the magnetic core and coefficient factor of force multiplicity, technical characteristics of levitation material element, set superheat temperature. A mathematical model has been compiled for based on the parameters of the current mode and forces from the equations of electrical, magnetic, mechanical and thermal circuits of the magnetic system. As a result, the main dimensions of the magnetic system and dimensionless quantities. Analytic expressions for the main dimensions, the specified values of the winding overheating temperature are taken into account, input and output parameters, the condition of uniformity of the magnetic field in the working air nom gap. The optimal values of the dimensions of the magnetic circuit, active resistors have been determined winding voltages are minimal, resulting in minimization of losses active capacities. [ABSTRACT FROM AUTHOR]

Log and Antilog Amplifiers are two very important functions in many electronic devices. Thus, in this article a new current mode (CM) log and antilog amplifier using current follower transconductance amplifier (CFTA) are presented. The logarithmic circuit is constructed using only one CFTA as active elements and one metal oxide semiconductor (MOS) transistor as diode operation and antilogarithmic amplifier circuit is implemented using only one CFTA as the active component, one MOS transistor as diode operation and two MOS transistor as active resistors. It provides the advantage of using MOS transistor instead of a resistor and diode that is beneficial to IC implementation in terms of space consideration which are suitable for IC implementation. These circuits provide logarithmic and antilogarithmic responses. Additionally, there is no demand to set selection criteria for components. The operation of the circuit in the current mode was verified by a nonideality study. PSPICE was used to test the scheme's functioning. The output curves coincide very close with the theoretical expectation. [ABSTRACT FROM AUTHOR]

This paper presents a novel low-voltage low power fully differential class AB current output stage with high linearity and unique current drive capability. The proposed circuit is based on a simple and efficient structure to obtain high linearity by minimising the channel length modulation effect and also avoids cascade structure to act best in low-voltage applications. Giving the complete analyses and equations of the circuit, its properties are verified by Cadence using TSMC 0.18 µm CMOS parameters. In order to study its performance at the presence of non-idealities, Pre-layout and Post-layout both plus Monte–Carlo simulations are also performed. Under±0.9 V supply and 35 µA output bias current, it can deliver the ever high output current of ±350 mA with THD of −49 dB and output impedance of 2.8 MΩ, which leads to a unique high current drive ratio (Ioutmax/Ibias) of 10,000 and low consumed power of 150 µw in pre-layout simulation. In post-layout plus Monte–Carlo simulation, the results will be as ±320 mA output current, −42 dB THD, 2.2 MΩ output impedance, 40 µA DC current of the output branch, 8000 current drive ratio and 160 µw consumed power. These remarkable results prove the proposed novel COS not only as the unique one in the world but Longley ahead of the yet second rank COS by some unbeatable ratios as 11300×,14×,4× and3× in FT, Ioutmax, (Ioutmax/power), and current drive, respectively, that promise to keep it as the lead one for many years in low-voltage/power ultra-high current applications. [ABSTRACT FROM AUTHOR]

Recent developments in multiplication circuits with fewer transistors, higher speed, and reduced energy consumption are lowering hardware costs. Approximate multiplication is used for fault-tolerant applications, such as image and signal processing. These applications offer considerable improvement at the cost of reduced accuracy. Compressors are the main component of any multiplier structure. In this work, the design of an approximate multiplier based on current mode, using 4:2 and 5:2 approximate compressors and current over scaling technique is suggested to reduce power consumption, delay, and hardware components compared to existing architectures. In the proposed approach for the design of compressor circuits, current mode binary converters with 32 nm CNTFET technology are used. This work is done in three steps: (1) converting input currents into voltage and creating multi-level voltages. (2) Implementing voltage level detector. (3) Generation of output current based on threshold voltage. The proposed technique uses less number of transistors. The simulation was done under HSPICE software and the efficiency of the compressors was compared in terms of delay, power, and power delay product (PDP). Based on the simulation results, the PDP value for 4:2 and 5:2 compressor circuits is calculated as 0.0097 and 0.0131 fJ, respectively. Then, an approximate multiplication of 8 × 8 using these compressors is designed for multiplying images under MATLAB software. This multiplier has achieved a good improvement in terms of PSNR and MSSIM (respectively 9.14 and 2.85%) compared to advanced approximate multipliers. Also, the proposed approach performs better in terms of accuracy, power consumption, and delay. [ABSTRACT FROM AUTHOR]

The relationship between the amount of energy consumption and the circuit speed to change the design efficiency is an important challenge in designing digital circuits. Adders are essential components of computing circuits that play an important role in computing speed. This article proposed a new design for a single-bit current mode full adder using the field effect transistors based on carbon nanotubes to enhance the speed and reduce the occupied space on the chip. The correct combination of the majority function, the current mirror technique, and the sum value on carry reduced the delay of all adder circuits. The simulations have been done by HSPICE software and based on the provided standard model of 32 nm with CNTFET technology. The proposed design has improved by 55% in terms of delay. The PDP level in the proposed design has decreased by 63% compared to the previous designs. [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

An adaptive biased architecture of voltage differencing transconductance amplifier (AB-VDTA) with high transconductance gain is proposed in this paper. The proposed AB-VDTA is very efficient in terms of power. The structure proposed involves of two units namely two transconductance amplifiers (TAs) and two squarer. The bias current of the TA is made to vary with a square relation of the differential input voltage. Therefore, the proposed structure provides tunable gain depending on the input differential voltage. The proposed AB-VDTA exhibits improved transconductance gain, transient characteristics, reduced standby power dissipation and linearity for large range of inputs. The mathematical formulation has been presented to establish the characteristics of the proposed AB-VDTA. The proposed structure of AB-VDTA is validated through SPICE simulations using 180 nm complementary metal oxide semiconductor (CMOS) technology. The proposed scheme has an edge over the existing ones as the outlined methods enhance the transconductance gain by increasing the bias current. The g m 1 values are observed to be 2.3 and 1.4 mS for proposed AB-VDTA and conventional VDTA, respectively, with the corresponding 3 dB frequencies 620 and 348 MHz. Therefore, 64% improvement in transconductance gain is recorded for same value of bias currents. The linear input range of TA1 is observed to be ± 1 5 0 mV and the overall linear range of the VDTA is ± 1 0 0 mV for the proposed AB-VDTA. The PVT analysis is carried out to show the effect of process corners. To check the robustness of the proposed VDTA, Monte Carlo analysis is performed, and results have been included in the form of histograms. As an application example, a current mode (CM) universal single input multiple output (SIMO) biquad filter is also designed using the proposed VDTA to show its usefulness, and a 2.7 times higher pole frequency is obtained at equal bias current. [ABSTRACT FROM AUTHOR]

This communication presents two new first order universal active filter configurations employing operational transconductance amplifiers (OTA) and use grounded capacitor which is prominently suitable for integrated chip (IC) fabrication. One of the proposed topologies provides voltage mode (VM) and transconductance mode (TCM) of operations while the other circuit provides current mode (CM) in addition with transresistance mode (TRM) filter functions. All three first order filter functions namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) are configurable with appropriate choice(s) of input voltage/current signals. An equal transconductor condition (which can be easily achieved) is required for the realization of APF functions. The proposed filter configurations possess high input impedance and high output impedance and also offer independent electronic tunability of pole frequency/cut-off frequency. The gain of filters realized in VM, TCM and TRM has independent electronic tunability feature and can be adjusted through transconductor. For the usability of proposed filters, multi-phase sinusoidal oscillator has also been demonstrated. To assure the workability of the proposed filter structures, PSPICE simulations with CMOS OTA implemented in 0.18 µm TSMC technology parameters has been used. Various simulation results including Monte-Carlo simulations, process corner analysis, total harmonic distortions (%THD) and temperature analysis have also been appended. Experimental results employing off-the-shelf IC LM13700 type OTAs have also been included to verify the theoretical propositions of first order universal filters and multiphase sinusoidal oscillators. [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment. [ABSTRACT FROM AUTHOR]

This paper presents a current-mode VCSEL driver (CMVD) implemented using 180 nm CMOS technology for application in short-range LiDAR sensors, in which current-steering logic is suggested to deliver modulation currents from 0.1 to 10 mApp and a bias current of 0.1 mA simultaneously to the VCSEL diode. For the simulations, the VCSEL diode is modeled with a 1.6 V forward-bias voltage and a 50 Ω series resistor. The post-layout simulations of the proposed CMVD clearly demonstrate large output pulses and eye-diagrams. Measurements of the CMVD demonstrate large output pulses, confirming the simulation results. The chip consumes a maximum of 11 mW from a 3.3 V supply, and the core occupies an area of 0.1 mm2.

Summary: This work proposes a link training based half‐rate dynamic current‐steering echo‐cancellation hybrid circuit topology for full‐duplex signaling that performs echo cancellation by deploying a bit error detection unit and backchannel adaptation. In addition, this work proposes a power‐efficient half‐rate dynamic current‐steering logic hybrid circuit for full‐duplex signaling over on‐chip interconnects for simultaneous transmission and reception. The half‐rate dynamic current‐steering hybrid circuit topology has low static power consumption compared with traditional current‐mode circuit topology implementations, thanks to the discrete nature of the current‐steering hybrid topology. The proposed scheme is implemented in 1.2 V, 65‐nm complementary metal‐oxide semiconductor (CMOS). The performance results show that the link training scheme sets the control bits for both the transmitter driver and hybrid circuit topology when the backchannel adaptation loop gets locked for 1‐ and 3‐mm interconnects for process, voltage, and temperature (PVT) variations. The proposed hybrid circuit topology is able to receive the required far‐end transmitted data with the link training scheme and has the differential recovered received signal voltage swing of 1.2 V for both 1‐ and 3‐mm interconnect at the 10‐Gb/s data rate. The total power consumption of the hybrid is 3 and 3.5 mW for 1‐ and 3‐mm interconnect with an energy efficiency of 0.6 and 0.7 pJ/bit, respectively, at 10‐Gb/s full‐duplex operation. [ABSTRACT FROM AUTHOR]

This work presents a flux-controlled memristor structure employing a Current-Controlled Current Differencing Transconductance Amplifier (CCCDTA) with a grounded capacitor. The proposed emulator's invariant and variant parts can be safely adjustable, showing promising characteristics of up to 1.5 MHz operating frequency. Furthermore, there is no need for an additional circuit, switching mechanism or changing the circuit topology for the changing of operation modes. To justify the performance of the emulator with incremental and decremental mode operations, a Monte Carlo and temperature analysis are validated using TSMC 0.18 µm technology under a symmetrical supply voltage of ±0.9 V. Furthermore, the workability of the proposed circuit is tested with commercial elements such as ALD1116, AD844 and LM13700. When compared with other studies, the presented emulator circuit demonstrates promising performance in various features. [ABSTRACT FROM AUTHOR]

The performance of Network-on-Chip depends a lot on the routers and interconnect circuits used in them. The gradual movement of technology towards nanometer scales has increased the core abilities, leading to an increase in delays and interconnect power consumption. As a result, %60 of the total current chip power consumption is related to the interconnect circuits. This paper has presented a simultaneous Bi-directional current-mode transceiver (SBCT-NoC) with two modes of operation, transmitter, and receiver. Two transceivers connected at both ends of an interconnect can use two-way communication through the same link. The proposed transceiver can significantly reduce the delay and power consumption of Network-on-Chip interconnects and increase the reliability using differential logic. This paper has simulated the circuits using 32-nanometer technology while considering the crosstalk noise effect. The results show the considerable advantage of the proposed method compared to previous interconnected circuit methods. [ABSTRACT FROM AUTHOR]

In this study, a novel DDCC-based two-integrator-loop universal active-C biquad with a companding process scheme is proposed. The proposed filter employs some processing blocks such as integrators and summing blocks. The use of the block diagram design procedure is attractive and systematic. The state space synthesis technique is utilized for the topology of the integrator design. Several advantages of the proposed filter are briefly expressed as: simultaneously realizing five second-order filter functions such as low-pass, high-pass, band-pass, all-pass and notch filter responses; offering resistorless realization; dissipating low power; having electronic tunability feature of its pole frequency and quality factor orthogonally; not suffering from disadvantages of the passive element matching problems. Some simulation results including frequency and time domain analysis results by using the PSpice program are carried out to confirm the theoretical ones. All the obtained simulation results are discussed. [ABSTRACT FROM AUTHOR]

The introduction of Add ‐ Differentiate IC, AD‐IC, a new integrated circuit, into schemes for realizing single input multiple output current mode filters is the motivation behind this paper. In the circuit structure of this filter with only one active device with a minimal number of transistors and five passive components are being used. Non ideal effects of the design are investigated and simulation results of the application, using TSMC 0.25 μm process parameters with ±1.25 V power supply voltage and the bias VB as 0.8 V resulting in 0.99 mW power dissipation for the entire filter, are also presented to confirm the theoretical analysis. With this new design technique, the tunabilities of the angular frequency (ω0) and quality factor (Q) can be performed independently. [ABSTRACT FROM AUTHOR]

This work presents a new active block called the differential current conveyor cascaded transconductance amplifier (DCCCTA) and implemented multi-mode biquadratic universal shadow filter. The frequency-hopping filter is implemented using a multi-mode universal shadow filter. The proposed circuit has two modes of operation: current mode (CM) and transadmittance mode (TAM). All-pass (AP), band-pass (BP), band-reject (BR), high-pass (HP), and low-pass (LP) responses are simultaneously accomplished. As intended, low input impedance for CM and high input impedance for TAM are acquired, while high output impedance is attained for both modes of operation. Inter-modulation distortion (IMD), percentage total harmonic distortion (%THD), and Monte Carlo analysis are also obtained. The theoretical results are verified using Cadence Virtuoso in 180 nm TSMC technology.

This paper describes a new CMOS current mode four-quadrant analog multiplier circuit. The proposed design is based on a high performance squarer cell, whose main core is realized by the up–down topology trans-linear loop using flipped voltage followers (FVF). The simulation results are verified by TSPICE simulator based on the BSIM3v3 transistor model for TSMC 0.18 µm CMOS process available from level 49 MOSIS at 25◦C with ± 0.75 V supply voltage. The proposed multiplier offers improved characteristics compared to the multipliers previously exposed in the literature. It has a wide dynamic range. The total harmonic distortion is about 0.42% at 1 kHz with peak-to-peak input current of 40 µA. The −3 dB bandwidth is more than 850 MHz and a maximum power consumption is of approximately 105 µW.

Compared to voltage mode circuits, current mode circuits have advantages such as large dynamic range, fast speed, wide frequency band, and good linearity. In recent years, the development of call flow modeling technology has been rapid and has become an important foundation for analog integrated circuits. In this paper, a current mode chaotic oscillation circuit based on current differential transconductance amplifier (CDTA) is proposed. This proposed circuit fully utilizes the advantages of current differential transconductance amplifier: a current input and output device with a large dynamic range, virtual ground at the input, extremely low input impedance, and high output impedance. The linear and non-linear parts of the proposed circuit operate in current mode, enabling a true current mode multi scroll chaotic circuit. Pspice simulation results show that the current mode chaotic circuit proposed can generate multi scroll chaotic attractors.

In a conventional current-mode dc–dc buck converter, two sensed inductor current signals are processed in three separate comparators to regulate the converter under various load conditions. These independent sensing currents and comparators not only consume large quiescent current and silicon areas but also cannot guarantee the accuracy of the current limit threshold. This article proposes a current-mode dc–dc buck converter with an accurate current limit using a multiplex pulsewidth modulation (PWM) comparator. Through a multiplex PWM comparator, only one sensing current and one comparator are required to process the inductor current information and complete the regulation of the converter under various load conditions. The response speed of overcurrent protection is also increased without consuming more power and silicon area. Moreover, by generating the zero temperature coefficient (ZTC) sensing current and adding ZTC reference current with slope compensation information, the accuracy of the current limit threshold is greatly improved under various temperatures in a wide input voltage range. The proposed buck converter with a multiplex PWM comparator was fabricated using a standard 1P3M 0.18 μm BCD (BiCMOS/DMOS) process and the experimental results show that the proposed scheme functions properly in the 5-A load range, and the current limit threshold also varies only 8.1% in the temperature range from −40 to 125 °C with the input voltage up to 60 V. [ABSTRACT FROM AUTHOR]

Copyright of Informacije MIDEM: Journal of Microelectronics, Electronic Components & Materials is the property of MIDEM Society and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

MCNP radiation transport output is post-processed by DRiFT, a D etector R esponse F unction T oolkit to simulate detailed nuclear instrumentation response. DRiFT can be used to assess the performance and potential limitations of scintillator, gas, and semiconductor detectors under a variety of simulated conditions not easily achievable in a laboratory setting. This work describes new updates in DRiFT for scintillator simulations which focus on the capability to simulate scintillators in current mode, an expansion of trigger options, and the ability to customize individual detector properties in a simulation. These improvements are designed to facilitate the ability to model large arrays of scintillator detectors with higher fidelity than was previously possible and are demonstrated in three examples. The first shows the difference between operating DRiFT in current and pulse mode. In the second example, which is intended to demonstrate deviations in individual detector performance, each detector has properties (PMT gain, optical transport, scintillation yield, etc.) that vary between detectors and are specified in DRiFT. A final example examines how DRiFT could be used to optimize digitizer settings in high rate measurements with split signals using the new common trigger option. • The ability to simulate current mode experiments has been implemented in DRriFT. • New features include common triggers and the ability to assign individual scintillator, PMT, and digitizer properties. • New features are demonstrated in several examples with scintillator arrays. [ABSTRACT FROM AUTHOR]

This paper presents the high-output-impedance current-mode multiphase sinusoidal oscillators (MSO) using voltage differencing current conveyor (VDCC)-based lossy integrators, which consist of one VDCC, one grounded capacitor, and two grounded resistors. The proposed oscillator can provide an odd-phase and even-phase system without the use of an additional amplifier. The frequency of oscillation (FO) is electronically tuned via the bias current without affecting the condition of oscillation (CO). The proposed oscillator is designed to obtain three-phase sinusoidal waveforms (n = 3). The effect of non-idealities of VDCC on the lossy integrator section is also investigated. The validity of the proposed circuit is demonstrated by PSPICE simulation using 0.18 µm TSMC CMOS process parameters with ±0.9V power supply. The frequency of oscillation obtained from the simulation is 1.43 MHz. The total harmonic distortions of the sinusoidal output currents IO1, IO2, and IO2 are 1.22%, 1.18%, and 0.57%. The IO1–IO2 and IO2–IO3 phase differences are approximately 121 and 119 degrees, respectively. The feasibility of the proposed MSO is also verified with experimental results using the VDCC constructed from the commercially available ICs (LT1288 and AD844) with ±5 V power supply. The results of PSPICE simulations and experiments are closely consistent with the theoretical expectation. [ABSTRACT FROM AUTHOR]

This study shows the electrodeposition of Fe-Cr-Ni alloys using the advantages of a stepped direct-current deposition in a Cr(III)-containing electrolyte, and its influence on the pH value. The resulting coatings are uniform and free of microcracks, with a Cr content around 30% and thicknesses above 10 µm. The influence of the current mode (direct current, stepped direct current, pulsed current) on pH development is investigated and correlated with the arising microstructure and alloy composition. Considering the current flow, it can be stated that pauses interrupt high overvoltage and restrain the pH increase at the cathode. The associated formation of chromium hydrides and their deposition onto the chromium layer, leading to cracking, is thus reduced. In this work, direct evidence for this theory and a suggestion for near-surface pH measurement during electrodeposition are presented. [ABSTRACT FROM AUTHOR]

In this paper, a new mixed-mode first-order universal filter configuration is presented that employs three operational transconductance amplifiers (OTAs) and one grounded capacitor (eminently suitable for IC chip fabrication). All three first-order generic filter functions, namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) in all the four possible modes, namely voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) can be realized. The proposed configuration offers high input impedance and high output impedance. The pole frequency of the filter can be controlled electronically by varying a single transconductance. Nonideal analysis of the proposed filter structure has also been carried out and the results have been compared with those obtained from ideal analysis. The performance of the presented filter configuration has been corroborated through PSPICE simulations as well as experimental results. The various simulation and experimental results validate the practical viability of the proposed configurations. [ABSTRACT FROM AUTHOR]

With rapid social and economic development, high-efficiency welding technology has become an important development direction in the field of welding. In recent years, scholars and professionals in many countries have devoted themselves to further increasing the welding efficiency by improving welding materials, welding process, and arc-welding equipment. The welding efficiency can be increased using two approaches: one is increasing the welding speed, the other is increasing the welding deposition rate. Considering these two methods, typical technologies such as multiwire submerged arc welding (SAW) and multiwire gas metal arc welding (GMAW) were proposed. A twin-arc integrated cold wire hybrid welding system was established. The mechanical effect of the cold wire position on the welding process was studied, including its effects on heating, melting, and weld surface formation. Results show that the melting of cold wire depends on the front end of the weld pool, and the melting effect of the weld pool on the cold wire is not sufficient when the cold wire is fed in front of two leading wires. The end of the cold wire makes contact with the bottom surface of the weld pool with the continuous feeding of the cold wire. Droplets melted at the wire ends are ejected and fall on the base metal surface to generate a globular spatter with the backward motion of the base metal. The thermal distribution on the side of the weld pool decreases as the cold wire is fed inside of the two leading wires. Hence, the flow of molten metal is affected, ultimately leading to an uneven weld formation. The cold wire is stably inserted into the weld pool when fed behind the two leading wires, representing the optimum cold wire position. Moreover, the deposition rates increase with an increase in the cold wire feed speed and show little change under two-pulse phase differences (in-phase and reverse-phase pulse differences). The effect of arc heating and melting on the cold wire was most intense at the in-phase pulse current, followed by the reverse-phase pulse current and subsequently direct current.

This work presents a flux-controlled memristor structure employing a Current-Controlled Current Differencing Transconductance Amplifier (CCCDTA) with a grounded capacitor. The proposed emulator’s invariant and variant parts can be safely adjustable, showing promising characteristics of up to 1.5 MHz operating frequency. Furthermore, there is no need for an additional circuit, switching mechanism or changing the circuit topology for the changing of operation modes. To justify the performance of the emulator with incremental and decremental mode operations, a Monte Carlo and temperature analysis are validated using TSMC 0.18 µm technology under a symmetrical supply voltage of ±0.9 V. Furthermore, the workability of the proposed circuit is tested with commercial elements such as ALD1116, AD844 and LM13700. When compared with other studies, the presented emulator circuit demonstrates promising performance in various features.

This brief communication presents two current feedback op‐amp (CFOA)‐based simple first‐order mixed‐mode universal filter topologies—one of them providing first‐order low‐pass (LP), high pass (HP), and all pass (AP)—all the three filters in voltage‐mode (VM)/trans‐admittance‐mode (TAM) while the other one realizing the quoted three functions in current‐mode (CM)/trans‐impedance‐mode (TIM). Except the all pass filter realization from the first configuration which needs a second CFOA also as gain‐of‐two amplifier, in all the remaining cases of both the configurations, only a single CFOA is needed. The other notable features of the circuits are employment of only three resistors and a grounded capacitor (as preferred for IC implementation) and the availability of independent tunability of the gain (H0) and cut‐off frequency/pole frequency (ω0) of all the three filters, in both the cases. In spite of not offering ideally infinite input impedance in VM/TAM mode and ideally zero input impedance in CM/TIM mode, the circuits still possess easy cascadability due to providing a voltage output from a low‐output impedance terminal W while the current output from the high output impedance terminal Z. Non‐ideal and sensitivity analyses have also been carried out. The workability of the proposed circuits has been demonstrated through PSPICE simulations and experimental results using the commercially available AD844‐type IC CFOA. [ABSTRACT FROM AUTHOR]

This article demonstrates a voltage differencing inverting buffered amplifier (VDIBA)-based resistorless flux-controlled memristor emulator circuit with tunability. Two VDIBA blocks serve as active components, and a grounded capacitor serving as a passive part. The proposed emulator design is devoid of multipliers and resistors through effective utilization of port relationships. Including tunability, the suggested emulator functions in both incremental and decremental modes. It accurately depicts the attributes of an ideal memristor up to 12.7 MHz and consumes a total power of 1.34 mW. The mathematical analysis is substantiated through Cadence simulation in 0.18- $\mu \text{m}$ Taiwan Semiconductor Manufacturing Company (TSMC) technology with the supply voltage of ±1 V. Nonideal, single/parallel, Monte-Carlo sampling and corner analysis were conducted to confirm circuit resilience. The nonvolatile nature of the presented emulator model has also been included. A breadboard prototype incorporating the ICs CA3080 and LT1193 are built to conduct an experimental demonstration. The experimental findings were consistent with the theoretical expectations and simulation results. [ABSTRACT FROM AUTHOR]

The Nevada National Security Site (NNSS), together with Los Alamos National Laboratory (LANL) and Lawrence Livermore National Laboratory, is developing a novel diagnostic to measure the reactivity of subcritical experiments (SCEs). This capability is known as neutron-diagnosed subcritical experiments (NDSEs). The decay of the fission gamma rays from the neutron-interrogated SCE is measured as a function of time with a large ($\sim 3$ -m diameter) detector wall consisting of 151 individual detector pixels. The data from this current mode measurement inform the neutron multiplication factor, $k_{\mathrm {eff}}$ , and thus the relative reactivity of the SCE. The NNSS developed the Gamma Array Simulation Toolkit (GAST) initially to help inform the design of the individual detector pixels and the 3.4-m diameter detector wall to be fielded as part of NDSEs. This toolkit is now being used to simulate and predict the performance of the final design of the individual detector pixels and the aggregate detector wall. Key detector characteristics evaluated from these simulations include impulse response, pulse height spectrum, number of photoelectrons per MeV, detector efficiency, and crosstalk between detector pixels. Collectively, the results of these simulations inform how well the fission gamma-ray die-off distribution from an NDSE measurement can be resolved. This is critical to determining the relative reactivity of the experiment. Furthermore, the GAST can be used to aid in the analysis of the experimental data from an NDSE measurement once the simulation has been benchmarked. [ABSTRACT FROM AUTHOR]

This study introduces a wideband LNTA-based receiver employing full current mode (FCM) signal transmission, leveraging a broadband and highly linear current-mode analog baseband (CMAB). The CMAB module comprises a shunt feedback low pass filter and a programmable gain amplifier (PGA) with wide bandwidth, utilizing a regulated CG current mirror design, enriched by gm-boosting methodology and positive feedback capacitance reutilization through an identical boost amplifier. Fabricated in 12 nm FinFET CMOS process, the FCM receiver attains notable characteristics including a baseband bandwidth of 1 GHz, a conversion gain of 30 dB, a noise figure of 5.2 dB, and an OIP3 of 14.6 dBm, while operating with a low supply voltage of merely 0.9 V. Simulation results validate the efficacy of this FCM receiver for wideband communication, effectively addressing the linearity constraints associated with low supply voltages and maximizing the advantages of FinFET technology in current-mode signal transmission. The total layout area is 0.484 mm 2. [ABSTRACT FROM AUTHOR]

This paper presents a power-efficient CMOS image sensor (CIS) for always-on object detection by using 1-bit log-gradient feature extraction in analog current domain. Compared with traditional image sensors with high-resolution ADCs, the proposed CIS extracts gradients in ratio form and generates feature maps at 1-bit resolution, which eliminates unnecessary background information and illumination-related data, and reduces the data computation in the later detector. The system containing the proposed CIS and back-end ANN detector is modeled with python and the simulation achieves an accuracy of 93.2 % for person detection. The CIS employs current mode divider and comparator to compute the gradient ratios. An accurate and configurable muti-input and muti-output (MIMO) current divider is proposed, composed of two cascaded modified second generation current controlled conveyors (M-CCCIIs). The proposed CIS was fabricated in a 0.18 μm standard CMOS process and realized a frame rate of 170 fps and an energy efficiency of 337 pJ/pixel in a power consumption of 1.1 mW. Experimental results show that the proposed CIS can realize the function of extracting log-gradients. [ABSTRACT FROM AUTHOR]

This study develops the control and driver for active Micro LED panel with chip-level design. The chip includes constant current circuit, digital-to-analog converter, SPI control interface, and active-matrix display control. The design process uses TSMC0.18um HVG2 CMOS technology, to realize 30 channels for micro LED driver. To reduce I/O pins, the input signals feed to the dynamic shift register in serial, and the results are loaded to the digital-to-analog converter (DAC) in parallel. The DAC module consists of R2R network, unity-gain buffer and sample-and-hold circuits. The DAC outputs with constant current for micro LED driving from voltage-to-current conversion. To reduce the number of DAC component, one DAC can share the common circuit to drive RGB LED of one pixel based on the selected current mirror structure. This chip can greatly reduce resistor and switches about 92% and 96% respectively, compared with the conventional R DAC structure. The measurements result with good linear for the current dimming control, which the test digital signals are generated by Verilog codes to estimate the gray current of this chip. [ABSTRACT FROM AUTHOR]

This paper presents a modified Current Follower Transconductance Amplifier (CFTA). It provides the essential features of high transconductance, wide bandwidth besides a wide linear range. It records the highest transconductance of 18.2 mS and power dissipation of 1.12 mW. Moreover, the linear range ( i F versus i x ) of CFTA is found as ± 8 0 μ A. All these essential performance parameters are found much better than the available literature. As an application, a novel second-order universal filter is implemented using the proposed CFTA. It is found that the performance of the filter improves with the use of the proposed CFTA. [ABSTRACT FROM AUTHOR]

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