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Neuromorphic computing, inspired by the human brain’s architecture, is expected to break the physical limits of transistors and von Neumann bottleneck. The multiple internal state variables of higher-order memristors (second-order or above) possess dynamic complexity and adaptability, enabling them to mimick the characteristics of biological neurons, which are very important building blocks for neuromorphic computing. This paper presents a simple neuron circuit containing a single second-order current-controlled locally-active memristor (LAM). The pinched hysteresis loop and DC V–I curve of the proposed second-order LAM show good odd symmetry. Applying small signal analysis method, we obtain the small-signal equivalent circuit of the neuron circuit, showing a LC parallel structure and an edge of chaos kernel in its locally-active domain. Also, we draw a parameter classification of the neuron circuit, showing four symmetrical edge of chaos domains, which plays an important role in biphasic action potentials. Finally, we demonstrate that the simple neuron circuit can produce monophasic action potentials, biphasic action potentials and co-existing neuromorphic phenomena via subcritical Hopf bifurcation with different input, verifying the simple circuit is suitable as artificial neurons. [ABSTRACT FROM AUTHOR]

The synapse‐based neuromorphic systems for deep neural network (DNN) require neuron read/update circuit blocks which specifications depend on the synapse components. In this study, we implemented and verified the dedicated circuit system to operate the three‐terminal analog synaptic memory cells, electrochemical random access memory (ECRAM), for multi‐bit analog neuromorphic computing. In addition, we analyzed the impact of the noise/offset generated by the neuron circuit systems and synapse cell arrays, which can affect the neuromorphic processing accuracy, by using the Modified National Institute of Standards and Technology database (MNIST) dataset. The experiments with MNIST datasets were conducted in two ways: by performing ideal inference simulations with MATLAB and experiments with the neuromorphic system board. The results of the ideal inference simulation and experiment were 97.4% and 96.92%, respectively. The accuracy of 97.31% was measured when the weight of the hidden layer was set with the fixed resistance values to confirm the effectiveness of the synapse cells. According to the results, the effects of synapse cells and neuron circuits to the processing accuracy were 0.09% and 0.39%, respectively. Also, this MNIST experiments verified that about 10% or smaller variations of weight values in the synapse cells lead to negligible effects on processing accuracy through the training and inference. [ABSTRACT FROM AUTHOR]

To mimic the homeostatic functionality of biological neurons, a split-gate field-effect transistor (S-G FET) with a charge trap layer is proposed within a neuron circuit. By adjusting the number of charges trapped in the Si3N4 layer, the threshold voltage (Vth) of the S-G FET changes. To prevent degradation of the gate dielectric due to program/erase pulses, the gates for read operation and Vth control were separated through the fin structure. A circuit that modulates the width and amplitude of the pulse was constructed to generate a Program/Erase pulse for the S-G FET as the output pulse of the neuron circuit. By adjusting the Vth of the neuron circuit, the firing rate can be lowered by increasing the Vth of the neuron circuit with a high firing rate. To verify the performance of the neural network based on S-G FET, a simulation of online unsupervised learning and classification in a 2-layer SNN is performed. The results show that the recognition rate was improved by 8% by increasing the threshold of the neuron circuit fired. [ABSTRACT FROM AUTHOR]

We present a capacitor-free, scalable CMOS neuron circuit that offers significant benefits, including a compact circuit area, low power consumption, adjustable firing threshold, and scalability. This circuit generates output pulses with widths that increase in proportion to the input current magnitude. It also features an adjustable firing threshold (1-6 nA), indicating the minimum input current required to trigger an output pulse. Fabricated using standard 180 nm CMOS technology, the circuit occupies an area of $200~{\mu }$ m2 and consumes 1.4 pJ of energy per output pulse.

Neuromorphic computing aims to achieve artificial intelligence by mimicking the mechanisms of biological neurons and synapses that make up the human brain. However, the possibility of using one reconfigurable memristor as both artificial neuron and synapse still requires intensive research in detail. In this work, Ag/SrTiO3(STO)/Pt memristor with low operating voltage is manufactured and reconfigurable as both neuron and synapse for neuromorphic computing chip. By modulating the compliance current, two types of resistance switching, volatile and nonvolatile, can be obtained in amorphous STO thin film. This is attributed to the manipulation of the Ag conductive filament. Furthermore, through regulating electrical pulses and designing bionic circuits, the neuronal functions of leaky integrate and fire, as well as synaptic biomimicry with spike-timing-dependent plasticity and paired-pulse facilitation neural regulation, are successfully realized. This study shows that the reconfigurable devices based on STO thin film are promising for the application of neuromorphic computing systems. [ABSTRACT FROM AUTHOR]

To mimic the homeostatic functionality of biological neurons, a split-gate field-effect transistor (S-G FET) with a charge trap layer is proposed within a neuron circuit. By adjusting the number of charges trapped in the Si3N4 layer, the threshold voltage (Vth) of the S-G FET changes. To prevent degradation of the gate dielectric due to program/erase pulses, the gates for read operation and Vth control were separated through the fin structure. A circuit that modulates the width and amplitude of the pulse was constructed to generate a Program/Erase pulse for the S-G FET as the output pulse of the neuron circuit. By adjusting the Vth of the neuron circuit, the firing rate can be lowered by increasing the Vth of the neuron circuit with a high firing rate. To verify the performance of the neural network based on S-G FET, a simulation of online unsupervised learning and classification in a 2-layer SNN is performed. The results show that the recognition rate was improved by 8% by increasing the threshold of the neuron circuit fired.

Spiking neural networks (SNNs) are considered a crucial research direction to address the "storage wall" and "power wall" challenges faced by traditional artificial intelligence computing. However, developing SNN chips based on CMOS (complementary metal oxide semiconductor) circuits remains a challenge. Although memristor process technology is the best alternative to synapses, it is still undergoing refinement. In this study, a novel approach is proposed that employs tools to automatically generate HDL (hardware description language) code for constructing neuron and memristor circuits after using Python to describe the neuron and memristor models. Based on this approach, HR (Hindmash–Rose), LIF (leaky integrate-and-fire), and IZ (Izhikevich) neuron circuits, as well as HP, EG (enhanced generalized), and TB (the behavioral threshold bipolar) memristor circuits are designed to construct the most basic connection of a SNN: the neuron–memristor–neuron circuit that satisfies the STDP (spike-timing-dependent-plasticity) learning rule. Through simulation experiments and FPGA (field programmable gate array) prototype verification, it is confirmed that the IZ and LIF circuits are suitable as neurons in SNNs, while the X variables of the EG memristor model serve as characteristic synaptic weights. The EG memristor circuits best satisfy the STDP learning rule and are suitable as synapses in SNNs. In comparison to previous works on hardware spiking neurons, the proposed method needed fewer area resources for creating spiking neurons models on FPGA. The proposed SNN basic components design method, and the resulting circuits, are beneficial for architectural exploration and hardware–software co-design of SNN chips. [ABSTRACT FROM AUTHOR]

Recently, research on artificial neuron circuits imitating biological systems has been actively studied. The neuron circuit can implement an artificial neural network (ANN) capable of low-power parallel processing by configuring a biological neural network system in hardware. Conventional CMOS analog neuron circuits require many MOSFETs and membrane capacitors. Additionally, it has low energy efficiency in the first inverter stage connected to the capacitor. In this paper, we propose a low-power neuron circuit with a multi-gate feedback field effect transistor (FBFET) that can perform integration without a capacitor to solve the problem of an analog neuron circuit. The multi-gate FBFET has a low off-current due to its low operating voltage and excellent sub-threshold characteristics. We replace the n-channel MOSFET of the inverter with FBFET to suppress leakage current. FBFET devices and neuron circuits were analyzed using TACD and SPICE mixed-mode simulation. As a result, we found that the neuron circuit with multi-gate FBFET has a low subthreshold slope and can completely suppress energy consumption. We also verified the temporal and spatial integration of neuron circuits. [ABSTRACT FROM AUTHOR]

Recently, research on artificial neuron circuits imitating biological systems has been actively studied. The neuron circuit can implement an artificial neural network (ANN) capable of low-power parallel processing by configuring a biological neural network system in hardware. Conventional CMOS analog neuron circuits require many MOSFETs and membrane capacitors. Additionally, it has low energy efficiency in the first inverter stage connected to the capacitor. In this paper, we propose a low-power neuron circuit with a multi-gate feedback field effect transistor (FBFET) that can perform integration without a capacitor to solve the problem of an analog neuron circuit. The multi-gate FBFET has a low off-current due to its low operating voltage and excellent sub-threshold characteristics. We replace the n-channel MOSFET of the inverter with FBFET to suppress leakage current. FBFET devices and neuron circuits were analyzed using TACD and SPICE mixed-mode simulation. As a result, we found that the neuron circuit with multi-gate FBFET has a low subthreshold slope and can completely suppress energy consumption. We also verified the temporal and spatial integration of neuron circuits.

• An integrate-and-fire (IF) neuron and a voltage level shifter circuit were fabricated and investigated for hardware-based SNN architectures. By observing a membrane potential of the IF neuron circuit, an integration and reset operation are successfully implemented. • In the fabricated IF neuron circuit, the number of output spikes are 2, 5, 10, and 20 at t pulses of 0.4 μs, 1 μs, 2 μs and 4 μs, respectively. The firing rate of the neuron circuit linearly increases as t pulse increases. • These measurement results demonstrate that the fabricated IF neuron circuit implements IF function and reset operation well with linear activation function. • The generation of high voltage pulses (>6 V) for a synaptic weight update are observed through the voltage level shifter circuit. An integrate-and-fire (IF) neuron and a voltage level shifter circuit were fabricated and investigated for hardware-based SNN architectures. To verify an IF function of neurons, the fabricated IF neuron circuit consists of a synapse, an integration/reset part, and a fire/trigger circuit. By observing a membrane potential of the IF neuron circuit, an integration and reset operations are successfully implemented. In the fabricated IF neuron circuit, the number of output spikes is 2, 5, 10, and 20 at t pulses of 0.4 μs, 1 μs, 2 μs and 4 μs, respectively. The firing rate of the neuron circuit linearly increases as t pulse increases. These measurement results demonstrate that the fabricated IF neuron circuit implements IF function and reset operation well with linear activation function. For suppression of a gate induced drain leakage (GIDL) at high drain voltages (>6 V), the voltage level shifter consists of MOSFETs with a lightly doped drain (LDD). The generation of high voltage pulses (>6 V) for a synaptic weight update is observed through the voltage level shifter circuit. [ABSTRACT FROM AUTHOR]