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High-bandwidth density and energy-efficient readout interfaces connecting the superconductor electronic (SCE) integrated circuits (IC) with room-temperature environments are essential for emerging quantum and classical superconducting computing applications, which motivate the design of cryogenic optical links. This work addresses four challenges in this communication link. First, a comprehensive link model, which consists of superconductor and semiconductor electronic/photonic components, is built to analyze the performance and energy efficiency of the link. Then, a novel cryogenic optical link based on the monolithic silicon photonic process and laser-forwarded coherent architecture is proposed to balance power consumption at cryogenic and room-temperature environments and improve overall energy efficiency. Next, an accurate device model is necessary for circuit design nowadays, while little is known about the transistor's behavior at cryogenic temperatures. A detailed theoretic analysis and device characterization of transistors from monolithic silicon photonic processes is presented. Following that, a proof-of-concept single-chip CMOS electronic-photonic cryogenic transmitter is designed and implemented in the 45RFSOI process. The link experiment at cryogenic temperatures with the direct drive from superconductor IC demonstrates its function, performance, and energy efficiency. Compared to the existing solution, our work shows the best energy efficiency by eliminating the extra discrete cryogenic amplifier requirement. Finally, a new type of EOPLL, including a boundless phase shifter-based phase rotator and dLev comparator-based phase estimator, is proposed to solve the inevitable time-varying phase offset issue in the laser-forwarded coherent architecture. A proof-of-concept coherent receiver with proposed EOPLL is designed and implemented in the 45SPCLO process.

Data center traffic continues to experience considerable growth due to the vast amount of data generated by cloud computing, augmented reality, and the internet of things and Intra-data center traffic makes up to 77% of the total traffic, so improvements in spectral efficiency, bandwidth and power consumption of data center interconnections contribute to overall energy efficiency. Intra-data center traffic interconnects aim for data rates above 200 Gbps per wavelength while reducing power consumption. Coherent links leveraging orthogonal polarization and quadrature modulation schemes are an energy-efficient alternative approach to commonly used intensity modulation direct detection (IMDD). A component to this vision is the realization of low-power, broadband optical receivers for quadrature phase shift keying (QPSK) or higher-order coherent waveforms.Improvements in energy efficiency through increased data rate and reduction in power consumption is also significantly affected by electronic-photonic integration. Co-packaged optics have been proposed as one approach to fulfill this demand by minimizing the high-speed I/O power consumption. Nevertheless, parasitic resistance, inductance and capacitance between electronic and photonic circuits deteriorates the high-speed performance and requires power hungry equalization, thereby eliminating improvements in energy efficiency. Consequently, packaging approaches that enable either monolithic or 3D integration of heterogeneous ICs, i.e. silicon photonic and electronic ICs, are promising approaches to improve performance.The focus of this work is to develop energy-efficient optical fiber communication links through studying the system architecture trade-offs, as well as integrated opto-electrical circuit design for the link implementation. Performance degradation due to packaging effects is also studied and quantized. Several fiber optic communication links have been designed and measured. The first monolithically integrated CMOS-Photonic coherent optical receiver was implemented and achieved 80 Gbps with 1.2 pJ/bit energy efficiency. The O-band receiver was redesigned to further improve the performance and achieved above 100 Gbps and a record energy efficiency below 1 pJ/bit. These results show the possibility to implement O-band coherent optical links to support 200 Gbps per wavelength below 10 pJ/bit for next generation intra data center applications.

Optical telecommunications currently cover a significant part in the digital data exchanges. The increasing rate of the exchanged data is pushing to the continuous improvement of involved technologies. Silicon photonics is a part of this development and aims to closely co-integrate optical and electronic components, using optoelectronics components as interfaces. This thesis is part of this theme and more particularly in the context of the characterization PIC25G technology developed by STMicroelectronics. It aims to bring optical connections directly to the servers of internet data centers in order to increase the overall data exchange performances.Like all technologies, it is necessary to perform a continuous monitoring of its performances through electrical and, here, optical characterization. But it is also important to be able to assess as accurately as possible the lifetime of these components under nominal conditions. A reliability study of silicon photonics components was therefore essential for STMicroelectronics. However, very few studies have been done on this topic. The objective of this thesis is to present the study of the reliability of the optoelectronic components used in telecommunications applications.This manuscript is organized into three main parts. The first will present in detail the context of this study, its challenges, and the objectives we set. A second part will be dedicated to the installation of an optoelectronic characterization bench and its validation, then will present the first tests performed on packaged components. The third chapter will present the different characterizations performed on photodetectors of PIC25G technology, we will show how the degradation of the performances observed during stress tests can be explained by a physical model that we will detail and validate. Finally, the perspectives opened by this work will be addressed in the more general context of the reliability of optoelectronic devices and integrated photonics., Les télécommunications par voie optique recouvrent de nos jours une part majoritaire dans l’échange des données numériques. L’augmentation des débits et des volumes de données échangées poussent à l’amélioration constantes des technologies qui les sous-tendent. La photonique sur silicium s’inscrit dans ce développement et vise à co-intégrer aux plus près les composants optiques et les composants électroniques en utilisant comme interface les composants optoélectroniques. Cette thèse s’inscrit dans cette thématique et plus particulièrement dans le cadre de la caractérisation de la technologie PIC25G développée par STMicroelectronics. Cette dernière a pour objectif de pouvoir amener les connexions optiques directement sur les serveurs des centres de données internet, pour ainsi augmenter les performances globales de l’échange des données.Comme toutes technologies, il est nécessaire de mener un suivi continu de ses performances par de la caractérisation électrique et, ici, optique. Mais il est aussi crucial de pouvoir évaluer le plus précisément possible la durée de fonctionnement de ces composants dans des conditions nominales. Une étude de fiabilité des composants de la photonique sur silicium était donc indispensable pour STMicroelectronics. Cependant, très peu d’études ont été menées sur ce sujet. L’objectif de cette étude est de présenter l’étude de la fiabilité des composants optoélectroniques visant les applications de télécommunication.Ce manuscrit est organisé en trois parties principales. La première d’entre elles présentera de façon détaillée le contexte de cette étude, ses enjeux ainsi que les objectifs que nous nous fixons. Une deuxième partie sera consacrée à la mise en place d’un banc de caractérisation optoélectronique, à sa validation, puis présentera les premiers tests réalisés sur des composants mis en boitier. Le troisième chapitre regroupera quant à lui les différentes caractérisations effectuées sur des photodétecteurs de la technologie PIC25G, nous y montrerons comment les dégradations de performance observées lors de tests de stress réalisés peuvent être expliquées par un modèle physique que nous détaillerons et validerons. Finalement, les perspectives ouvertes par ces travaux seront abordées non seulement par rapport à la problématique de STMicroelectronics mais aussi dans le cadre plus général de la fiabilité des dispositifs optoélectroniques et photoniques intégrés.