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A comparative study on SiC MOSFETs is carried out with an emphasis on the design of integrated Schottky barrier diode (SBD) with numerical simulations by Sentaurus TCAD. Compared with the conventional SiC MOSFET (C-MOS) and the conventional SBD-embedded SiC MOSFET (C-MOSBD), the MOSFET (M-MOSBD) features a hybrid doping mesa above the JFET region where a Schottky contact is formed, which exhibits a superior trade-off between the on-state resistance (R dson) and the reverse transfer capacitance (C rss). Besides, the integrated diode in M-MOSBD renders a better trade-off between OFF-state junction field (E Smax) and forward voltage (V F) when compared to C-MOSBD and the conventional junction barrier Schottky diode (JBS), i.e., the external SBD of C-MOS. In the double pulse test simulation, C-MOS exhibited the largest switch loss followed by C-MOSBD, and M-MOSBD is the smallest. Therefore, in power switching applications where reverse conduction is required, M-MOSBD greatly reduces the chip area while presenting better characteristics. [ABSTRACT FROM AUTHOR]

A number of studies have focused on Insulated Gate Bipolar Transistor (IGBT) junction temperature prediction methods. Some methods introduce extra circuits or sensors for an invasive prediction. However, the most of current methods hardly consider the situation that the junction temperature prediction may be affected by the IGBT degradation after long term operation. In this paper, the neural network using DC link voltage, switching frequency, load current and Negative Thermal Coefficient thermistor (NTC) temperature as inputs is proposed for junction temperature online prediction. The neural network training is completed through the IGBT module tests. The accelerated aging tests are then performed to validate the neural network results over lifetime. The static and transient working conditions are respectively validated at different aging degrees. Finally, a neural network with good accuracy could be achieved by a series of experiments considering IGBT device degradation. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) MOSFET chips are often connected in parallel in a module to increase the current rating. However, the current capability is degraded due to unbalanced current and temperature distributions which affect the avalanche processes particularly in extreme operating conditions. To obtain the root cause of the degradation and identify the dominant factors, single-pulse avalanche testing is carried out in this study, and TCAD simulation is used for mechanism analysis. It is revealed that electrothermal parameters have different effects on current sharing in different stages of avalanching. The corresponding failure mechanisms are analyzed, and the main cause of avalanche failure with parallel devices is found to be the difference in breakdown voltage. Device with smaller BV shares more current as well as more heat, which fails first eventually. To resolve such issues, proper device screening/paring should be carried out. The findings are helpful for a better understanding of avalanche capability degradation in parallel devices application. • To determine the influence of parameters inconsistency and identify the dominant factors in the parallel avalanche capability. • To obtain the root cause of the degradation, single-pulse avalanche testing and TCAD simulation are carried out. • The main cause of avalanche failure with parallel devices is found to be the difference in breakdown voltage. • The research has guiding significance in power module designs and application of SiC MOSFET devices. [ABSTRACT FROM AUTHOR]

In order to obtain junction temperature of insulated-gate bipolar transistor (IGBT) on electric vehicle, a number of studies have proposed junction temperature (T j) estimation methods. However, some of these methods require additional circuits which lead to cost increase, some methods simulate the IGBT thermal process with thermal model, which induces a deviation between real functional results and simulation, and the other algorithm based methods may involve upgrading the main control unit (MCU) with increased costs. This paper proposes a method of IGBT T j estimation with regression analysis. The presented method firstly extracts the most sensitive factors from IGBT power loss model, and then the factors are applied in a data fitting function to characterize T j. After that, the mentioned fitting function is validated by regression analysis with statistics Anderson – Darling (AD) and P -value. Finally the T j estimation fitting function is demarcated by the negative thermal coefficient (NTC) measured temperature (T NTC). With the method using T NTC demarcation, the error bandwidth between estimated T j and measured T j is 3.4 °C in total. Compared with the T j estimation without T NTC demarcation, the error bandwidth of T j decreased from 6.9°C to 3.4 °C. The T j estimation method with T NTC demarcation is efficient for an online T j estimation of IGBT modules without increased costs. [ABSTRACT FROM AUTHOR]