111 results on '"Bagherzadeh, Nader"'
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2. Application Characterization for Near Memory Processing
3. Supervised Machine-Learning Algorithms in Real-time Prediction of Hypotensive Events
4. NoC Design Methodologies for Heterogeneous Architecture
5. Partition Pruning: Parallelization-Aware Pruning for Dense Neural Networks
6. Accelerating HPC Applications Using Computational Storage Devices
7. Efficient Deep Neural Networks for Edge Computing
8. A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks
9. A Radiation Hard Sense Circuit for Spin Transfer Torque Random Access Memory
10. Power and Performance Optimal NoC Design for CPU-GPU Architecture Using Formal Models
11. Catalina: In-Storage Processing Acceleration for Scalable Big Data Analytics
12. Thermal TSV Optimization and Hierarchical Floorplanning for 3-D Integrated Circuits.
13. CompStor: An In-storage Computation Platform for Scalable Distributed Processing
14. HTF-MPR: A heterogeneous TensorFlow mapper targeting performance using genetic algorithms and gradient boosting regressors
15. Simulation-Based Evaluation Strategy for Task Mapping Approaches in WNoC Platforms
16. Divisible Load Scheduling of Image Processing Applications on the Heterogeneous Star Network Using a new Genetic Algorithm
17. Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks
18. Online monitoring and adaptive routing for aging mitigation in NoCs
19. CoBRA: Low cost compensation of TSV failures in 3D-NoC
20. Efficient Mitchell’s Approximate Log Multipliers for Convolutional Neural Networks.
21. First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip.
22. Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption.
23. LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification.
24. A Compositional Approach for Verifying Protocols Running on On-Chip Networks.
25. AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCs.
26. Ultra-Efficient Fuzzy Min/Max Circuits Based on Carbon Nanotube FETs.
27. STABLE: Stress-Aware Boolean Matching to Mitigate BTI-Induced SNM Reduction in SRAM-Based FPGAs.
28. Capacitive Coupling Mitigation for TSV-based 3D ICs
29. An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip
30. TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip
31. ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects.
32. A General Fault-Tolerant Minimal Routing for Mesh Architectures.
33. SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs.
34. Deadlock Verification of Cache Coherence Protocols and Communication Fabrics.
35. A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs.
36. Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation.
37. Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks.
38. Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs.
39. Coupling Mitigation in 3-D Multiple-Stacked Devices.
40. Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip.
41. A formally verified deadlock-free routing function in a fault-tolerant NoC architecture
42. LATEX: New Selection Policy for Adaptive Routing in Application-Specific NoC
43. Design and Analysis of a Mesh-based Wireless Network-on-Chip
44. Design and Evaluation of a High Throughput QoS-Aware and Congestion-Aware Router Architecture for Network-on-Chip
45. Load Balancing for Data-Parallel Applications on Network-on-Chip Enabled Multi-processor Platform
46. A Wireless Network-on-Chip Design for Multicore Platforms
47. Message Driven Programming with S-Net: Methodology and Performance
48. Congestion-aware Network-on-Chip router architecture
49. Area and Power-efficient Innovative Network-on-Chip Architecurte
50. A scalable delay insensitive asynchronous NoC with adaptive routing
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