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This article proposes a methodology for critical path selection and delay sensor insertion for aging monitoring in field-programmable gate arrays (FPGAs). The aging information can be used to reconfigure FPGAs to achieve better performance or wear leveling. To filter out the paths aging less aggressively, our methodology decides based on both physical-level parameters [e.g., path delay, process variation, temperature, static stress (duty cycle), and dynamic stress (switching activity) as well as aging-relevant parameters (e.g., fan-out, and endpoint physical location)]. After selection of an optimal set of paths, age sensors, introduced in our earlier work, are placed in a distributed fashion throughout the FPGA area to provide aging information of its various parts as they are being used. Accurate aging models for FPGAs are required to determine the contribution of the above-mentioned parameters in aging. In this article, ASICs’ aging models are adapted for FPGAs through measurement-based fitting approach. The experimental results using various benchmarks reveal that our algorithm selects paths with a minimum error. [ABSTRACT FROM AUTHOR]

In this article, we propose a fine-grained FPGA aging mitigation method. Our method focuses on Look Up Tables (LUTs) on which Boolean functions are mapped. Based on our observations, for any configuration, even if it is carefully selected, a number of LUT transistors experience severe stress rates. Therefore, an algorithm is presented to select several alternative configurations for each LUT. Alternative configurations are obtained by LUT input reordering. These alternative configurations are rotationally loaded into the FPGA. Experimental results shows that our method achieves 263 and 14.1 percent Mean Time To Failure (MTTF) improvement for Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI), respectively. Additionally, due to changing only local routings, our method imposes up to 1 percent performance overhead to the systems. [ABSTRACT FROM AUTHOR]

Having an automatic tool capable of completing all steps of debugging including correction specially for complex designs such as modern processors is ideal for every debugging engineer. Although in theory, quantified Boolean formulas (QBFs) can be used to formulate this class of problems effectively, current solvers are still too immature for accomplishing this goal. In this paper, we propose a scalable symbolic simulation-based method utilizing QBF to correct the candidate bug locations in abstract formal models. We assume that candidate bug locations are determined already, the bug is located in bit-level logic, and the input arguments are known. We define correcting functions and adjust their parameters by formulating the problem as QBF and solving it using symbolic simulation-based method. To further improve scalability, we propose dynamic pruning which breaks the main problem into several smaller subproblems. The efficiency of the proposed method is proved by solving problems for which existing methods are not capable of providing results. [ABSTRACT FROM AUTHOR]

The increasing demand for lower power forces designers to use sophisticated power management strategies such as multivoltage and power gating which are often accompanied with many design bugs. Correcting such bugs can be a timeconsuming process that requires considerable manual efforts. In this paper, we propose a scalable automated method for correcting dynamic power management architectures by an incremental SAT-based mechanism. First, an initial counterexample (CEX) is generated by checking the equivalency between the specification model of the processor and its buggy implementation model. Then, we find two candidate solutions instead of one to satisfy this CEX. If two solutions are not equivalent, we generate new CEX in an iterative process which effectively converges into the final solution. The proposed method enables designers to correct multiple bugs such as missing isolation cells between two power domains, disordering in the sequence of control signals, error in the data restoring or saving, and powering off in always-on domains which are not addressed by existing methods. We have shown the effectiveness of our method on modern processors supporting complex power management mechanisms. The results confirm that our proposed method, respectively, reduces symbolic simulation steps and runtime by 2.33× and 47.93× compared to the state-of-the-art methods. [ABSTRACT FROM AUTHOR]

Although using presilicon information in postsilicon debugging phase seems interesting, space and time limitations of existing formal verification tools restrict the possibility of this idea. In this paper, the effective usage of presilicon information to enhance postsilicon trace signal selection in modern processors is discussed. Furthermore, a novel architecture for dynamic per-cycle selection of signals based on the present instruction is implemented and synthesized. In presilicon phase, first, a set of controlling signals and their corresponding rules are extracted manually. Based on these rules, a set of data from model is extracted using an automatic formal method, which determines which signals should be traced at postsilicon according to the values of controlling signals. This mechanism alone results in an average of 79% and 54% bits to be pruned from the traceable signals for Leon3 and multithreaded DLX processors and 86% and 75% improvement when used in conjunction with traditional methods, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a highly scalable sensor design for late transition detection in FPGA based platforms. Transition delays occur because of aging mechanisms such as Biased Temperature Instability (BTI) and Hot Carrier Injection (HCI). We propose a sensor clock (SCLK) that is a function of minimum slack time of a set of paths selected for age monitoring. There will be one such clock for many sensors as are needed in an entire FPGA. Our proposed sensor architecture makes it possible for a single SCLK to be shared by all sensors. Additionally, the proposed sensor occupies one slice (basic FPGA logic block), which leads to low area, power, and performance overhead. Using Artix-7-based board, experimental results demonstrate that the proposed aging sensor detects aging earlier than existing sensors and provides less power and performance overheads. [ABSTRACT FROM AUTHOR]