148 results on '"Navabi, Zainalabedin"'
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2. AFTAB: A RISC-V Implementation with Configurable Gateways for Security
3. n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator
4. Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester
5. Integrating an Interconnect BIST with Crosstalk Avoidance Hardware
6. Online Testing of a Row-Stationary Convolution Accelerator
7. Compensating Detection Latency of FPGA Scrubbers with a Collaborative Functional Hardware Duplication
8. Built-In Predictors for Dynamic Crosstalk Avoidance
9. ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links
10. DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation
11. Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations
12. An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements
13. From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization
14. SCOAP-based Directed Random Test Generation for Combinational Circuits
15. Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment
16. An ESL Environment for Modeling Electrical Interconnect Faults
17. Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme
18. Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling
19. Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information.
20. LUT Input Reordering to Reduce Aging Impact on FPGA LUTs.
21. Near-Optimal Node Selection Procedure for Aging Monitor Placement
22. A novel SAT-based ATPG approach for transition delay faults
23. Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach
24. Online Profiling for cluster-specific variable rate refreshing in high-density DRAM systems
25. TruncApp: A truncation-based approximate divider for energy efficient DSP applications
26. Early prediction of timing critical instructions in pipeline processor
27. An improved scheme for pre-computed patterns in core-based SoC architecture
28. Universal mitigation of NBTI-induced aging by design randomization
29. ESL design with RTL-verified predesigned abstract communication channels
30. Optimistic clock adjustment for preventing Better-than-worst-case violations
31. Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors.
32. Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model
33. Automatic Correction of Dynamic Power Management Architecture in Modern Processors.
34. HDLs evolve as they affect design methodology for a higher abstraction and a better integration
35. Multi-valued logic test access mechanism for test time and power reduction
36. Application-specific power-aware mapping for reconfigurable NoC architectures
37. Signature oriented model pruning to facilitate multi-threaded processors debugging
38. Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation
39. Low power scheduling in high-level synthesis using dual-Vth library
40. A heuristic path selection method for small delay defects test
41. Preemptive multi-bit IJTAG testing with reconfigurable infrastructure
42. Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors.
43. SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs.
44. Back-annotation of gate-level power properties into system level descriptions
45. An off-line MDSI interconnect BIST incorporated in BS 1149.1
46. Automatic correction of certain design errors using mutation technique
47. Improving polynomial datapath debugging with HEDs
48. Homogeneous many-core processor system test distribution and execution mechanism
49. RTL datapath optimization using system-level transformations
50. Assertion-based verification for system-level designs
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