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Recently, the development of quantum chips has made great progress – the number of qubits is increasing and the fidelity is getting higher. However, qubits of these chips are not always fully connected, which sets additional barriers for implementing quantum algorithms and programming quantum programs. In this paper, we introduce a general circuit optimizing scheme, which can efficiently adjust and optimize quantum circuits according to arbitrary given qubits’ layout by adding additional quantum gates, exchanging qubits and merging single-qubit gates. Compared with the optimizing algorithm of IBM’s QISKit, the quantum gates consumed by our scheme is 74.7%, and the execution time is only 12.9% on average.

Automated techniques for analysis and optimization of finite-precision computations have recently garnered significant interest. Most of these were, however, developed independently. As a consequence, reuse and combination of the techniques is challenging and much of the underlying building blocks have been re-implemented several times, including in our own tools. This paper presents a new framework, called Daisy, which provides in a single tool the main building blocks for accuracy analysis of floating-point and fixed-point computations which have emerged from recent related work. Together with its modular structure and optimization methods, Daisy allows developers to easily recombine, explore and develop new techniques. Daisy’s input language, a subset of Scala, and its limited dependencies make it furthermore user-friendly and portable.

Cross-interference may happen when applications share a common physical machine, affecting negatively their performances. This problem occurs frequently when high performance applications are executed in clouds. Some papers of the related literature have considered this problem when proposing strategies for Virtual Machine Placement. However, they neither have employed a suitable method for predicting interference nor have considered the minimization of the number of used physical machines and interference at the same time. In this paper, we present a solution based on the Iterated Local Search framework to solve the Interference-aware Virtual Machine Placement Problem for HPC applications in Clouds (IVMP). This problem aims to minimize, at the same time, the interference suffered by HPC applications which share common physical machines and the number of physical machines used to allocate them. Experiments were conducted in a real scenario by using applications from oil and gas industry and applications from the HPCC benchmark. They showed that our method reduced interference in more than 40%, using the same number of physical machines of the most widely employed heuristics to solve the problem.

The purpose of this article is to conduct research on graphics processing (GP) methods based on DL in the context of big data (BD). First, this article studies the characteristics of current BD and investigates related applications. Then based on DL, this article proposes a method of processing graphics content. This method uses three different DL network structures to extract graphic features. In this paper, the OpenMP parallel model is used to optimize the graph search algorithm in parallel on the CPU platform, and the algorithm is optimized in parallel by using the principle of program locality, reducing synchronization overhead and load balancing. Thirdly, in view of the irregularity of the memory access of the graph search algorithm, the FPGA algorithm hardware accelerator is customized using BD technology. Finally, it introduces the development tools of DL algorithm hardware acceleration, and compares them with traditional processing methods. Comparative experiments show that the image processing method based on DL proposed in this paper has an average recognition rate of about 10% higher than traditional processing methods, and has better results, providing an important reference for the development of image processing.

This paper presents the impact of using quantization on the efficiency of multi-class text classification in the training process of a support vector machine (SVM). This work is focused on comparing the efficiency of SVM model trained using reduced precision with its original form. The main advantage of using quantization is decrease in computation time and in memory footprint on the dedicated hardware platform which supports low precision computation like GPU (16-bit) or FPGA (any bit-width). The paper presents the impact of a precision reduction of the SVM training process on text classification accuracy. The implementation of the CPU was performed using the OpenMP library. Additionally, the results of the implementation of the GPGPU using double, single and half precision are presented.

This paper reviews and analyzes different low-power saving techniques in GPUs. The survey attempts to analyze and understand the architectural aspect of novel GPU design suggestions that researchers have come up with to provide cost-effective solutions for increasing GPU power numbers. These power-saving insights venture into the space of system-level low-power implementations, while others exploit the application-dependent optimizations, thereby making this study an interesting mix between architecture, application, and system-level implementations. This paper also focuses on underlining the impact of any power-saving feature in terms of area overhead and timing constraint latencies. This gives the reader a complete picture of the scope and challenges in the low-power GPU exploration space. The study is limited by time and hardware resources, and there is an excellent opportunity to quantify reviewed techniques and results to be compared against a common baseline.

With the development of Wi-Fi technology, the IEEE 802.11n series communication protocol and the subsequent wireless LAN protocols use multiple-input multiple-output (MIMO) and orthogonal frequency division multiplexing (OFDM) and other technologies. Channel characteristics between Wi-Fi transceivers can be estimated at the physical layer and stored in the form of channel state information (CSI). In this paper, we propose a CSI-based indoor ranging method using a gray prediction method that generates CSI predictions. This paper also provides experimental comparisons of our proposed data generation method with existing indoor ranging methods. Experimental results show that the proposed data generation approach achieves significant ranging accuracy improvement over using an effective CSI ranging method, while it incurs much less computational complexity. Meanwhile, the proposed method also can obtain more accurate ranging results in corner areas of the indoor environment where Wi-Fi signals cannot be obtained.

It could be of great difficulty and cost to directly apply complex deep neural network to mobile devices with limited computing and endurance abilities. This paper aims to solve such problem through improving the compactness of the model and efficiency of computing. On the basis of MobileNet, a mainstream lightweight neural network, we proposed an Adaptive Tensor-Train Decomposition (ATTD) algorithm to solve the cumbersome problem of finding optimal decomposition rank. For its non-obviousness in the forward acceleration of GPU side, our strategy of choosing to use lower decomposition dimensions and moderate decomposition rank, and the using of dynamic programming, have effectively reduced the number of parameters and amount of computation. And then, we have also set up a real-time target network for mobile devices. With the support of sufficient amount of experiment results, the method proposed in this paper can greatly reduce the number of parameters and amount of computation, improving the model’s speed in deducing on mobile devices.

Sequential logic encryption is a countermeasure against reverse engineering of sequential circuits based on modifying the original finite state machine of the circuit such that the circuit enters a wrong state upon being reset. A user must apply a certain sequence of input patterns, i.e., a key sequence, for the circuit to transition to the correct state. The circuit then remains functional unless it is powered off or reset again. Most sequential encryption methods require the correct key to be applied only once. In this paper, we propose a novel Sporadic-Authentication-Based Sequential Logic Encryption method (SANSCrypt) that circumvents the potential vulnerability associated with a single-authentication mechanism. SANSCrypt adopts a new temporal dimension to logic encryption, by requiring the user to sporadically perform multiple authentications according to a protocol based on pseudo-random number generation. We provide implementation details of SANSCrypt and present a design that is amenable to time-sensitive applications. In SANSCrypt, the authentication task does not significantly disrupt the normal circuit operation, as it can be interrupted or postponed upon request from a high-priority task with minimal impact on the overall performance. Analysis and validation results on a set of benchmark circuits show that SANSCrypt offers a substantial output corruptibility if the key sequences are applied incorrectly. Moreover, it exhibits exponential resilience to existing attacks, including SAT-based attacks, while maintaining a reasonably low overhead.

Since observational astronomy has turned into data-driven astronomy recently, analyzing this huge data effectively to extract useful information is becoming an important and essential task day by day. In this paper, we developed a neural network model to analyze redshift data of million of extragalactic objects. In order to do that, two different approaches for faster training of neural networks have been proposed. The first approach deals with the training model using Lipschitz-based adaptive learning rate in a single node/machine whereas the second approach discusses processing astronomy data in a multinode clustered environment. This approach can scale up to accommodate multiple nodes when necessary to handle bulk data using Apache spark and Elephas. Additionally, this paper also addresses the scalability and storage issue by implementing the model on the cloud. We used the distributed processing capability of the spark that reads data directly from HDFS (Hadoop Distributed File System) of multiple machines and our experimental results show that using these approaches we can reduce training time and CPU time tremendously which is a crucial requirement while dealing with the extensive dataset. Although we have tested our experiment on a subset of huge data it can be scaled to process data of any size as well without much hurdle.

It is expected the massive release of quantum computers in the near future. Quantum computers can easily break the crypto schemes, which are used in practice. Therefore, classical encryption systems have become vulnerable to quantum computer-based attacks. This involves the research efforts that look for encryption schemes that are immune to quantum computer-based attacks. This paper describes the digital signature schemes, which are safe against quantum computer attacks, but these schemes have different efficiency problems. The signature size of the scheme is very large and one-way function are used many time during the signature process. The paper offers the ways of reducing the signature size and acceleration the process of using one-way functions. It is offered to integrate the quantum key distribution algorithms into the scheme. It is also offered to use Blake family hash function as the one-way function.

Order-batching is an important methodology in warehouse material handling. This paper addresses three identified shortcomings in the current literature on order-batching optimization. The first concerns the overly large dependence on conventional warehouse layouts. The second is a lack of proposed optimization methods capable of producing approximate solutions in minimal computational time. The third is a scarcity of benchmark datasets, which are necessary for data-driven performance evaluation. This paper introduces an optimization algorithm, SBI, capable of generating reasonably strong solutions to order-batching problems for any warehouse layout at great speed. On an existing benchmark dataset for a conventional layout, Foodmart, results show that the algorithm on average used 6.9% computational time and 105.8% travel cost relative to the state of the art. New benchmark instances and proposed solutions for various layouts and problem settings were shared on a public repository.

The development of machine learning methods has given a new impetus in the field of solving inverse mechanics problems. Many papers show the successful application of well-proven techniques of ultrasonic, magnetic, thermal non-destructive testing with the latest methods based on machine learning and neural networks, in particular. This paper demonstrates the potential of applying the machine learning methods to the task of two-dimensional ultrasonic imaging. We have built a model of acoustic ultrasonic non-destructive testing that simulates the sounding of the inspecting object and the propagation of an ultrasonic wave in it. In the course of the set of numerical experiments we have created a data set for training of convolutional neural networks. The presented results show a high degree of informativeness of the ultrasonic response and its agreements to the real form of the internal defect inside the inspection object.

Burn probability maps (BPMs) are among the most effective tools to support strategic wildfire and fuels management. In such maps, an estimate of the probability to be burned by a wildfire is assigned to each point of a raster landscape. A typical approach to build BPMs is based on the explicit propagation of thousands of fires using accurate simulation models. However, given the high number of required simulations, for a large area such a processing usually requires high performance computing. In this paper, we propose a multi-GPU approach for accelerating the process of BPM building. The paper illustrates some alternative implementation strategies and discusses the achieved speedups on a real landscape.

Picnic is a post-quantum digital signature scheme, where the security is based on the difficulty of inverting a symmetric block cipher and zero-knowledge proofs. Picnic is one of the alternate candidates of the third round of the standardization process. Hence, it could be standardized in case of any weakness found in the round three candidates. Based on our paper at the 23rd Euromicro Conference ([6]), we found an optimization, which reduces memory usage to make it usable on IoT devices. This paper focusses on approaches for the implementation of this optimization. As a proof-of-concept, we implemented our implementation of Picnic on a ST Nucleo-L476RG and measured the cycles of the implementation.

With image processing, robots acquired visual perception skills; enabling them to become autonomous. Since the emergence of Artificial Intelligence (AI), sophisticated tasks such as object identification have become possible through inferencing Artificial Neural Networks (ANN). Be that as it may, Autonomous Mobile Robots (AMR) are Embedded Systems (ESs) with limited on-board resources. Thus, efficient techniques in ANN inferencing are required for real-time performance. This paper presents the process of optimizing ANNs inferencing using tensor-based optimization on embedded Graphical Processing Unit (GPU) with Computer Unified Device Architecture (CUDA) platform for parallel acceleration on ES. This research evaluates renowned network, namely, You-Only-Look-Once (YOLO), on NVIDIA Jetson TX2 System-On-Module (SOM). The findings of this paper display a significant improvement in inferencing speed in terms of Frames-Per-Second (FPS) up to 3.5 times the non-optimized inferencing speed. Furthermore, the current CUDA model and TensorRT optimization techniques are studied, comments are made on its implementation for inferencing, and improvements are proposed based on the results acquired. These findings will contribute to ES developers and industries will benefit from real-time performance inferencing for AMR automation solutions.

A significant concern for the candidate schemes of the NIST postquantum cryptography standardization project is the protection they support against side-channel attacks. One of these candidate schemes currently in the NIST standardization race is the Dilithium signature scheme. This postquantum signature solution has been analyzed for side channel attack resistance especially against timing attacks. Expanding our attention on other types of side-channel analysis, this work is focused on correlation based differential side channel attacks on the polynomial multiplication operation of Dilithium digital signature generation. In this paper, we describe how a Correlation Power Attack should be adapted for the Dilithium signature generation and describe the attack process to be followed. We determine the conditions to be followed in order for such an attack to be feasible, (isolation of polynomial coefficient multiplication inpower traces) and we create a power trace profiling paradigm for the Dilithium signature scheme executed in embedded systems to showcase that the conditions can be met in practice. Expanding the methodology of recent works that mainly use simulations for power trace collection, in this paper, power trace capturing and profiling analysis of the signature generation process was succesfully done on a, noisy, Commercial off-the-shelf ARM Cortex-M4 embedded system.

Parallel software system testing is very difficult because the number of states expands sharply caused by parallel behaviors. In this paper, a testing sequence generation method is proposed, target at full covering tested behaviors and related behaviors over all execution paths. Because of state spaces of parallel software systems are often large, this paper focuses on the state space sub-graph, contained all firing of tested and related behaviors, of system model. Firstly, the software system is modeled with Colored Petri Net (CPN), called system model (SM), and every tested behavior or related behavior is modeled also with CPN, called Behavior Model Unit (BMU). Then, the method proposes mapping operation, intersection operation, and so on to finally realize the generation of test sequence. Practices show that this method is efficient, which could achieve full coverage.

With the growing use of online digital media, it is becoming increasingly challenging to protect copyright and intellectual property. Data hiding techniques like digital watermarking can be used to embed data within a signal for purposes such as digital rights management. This paper investigates a watermarking technique for digital images using QR codes. The advantage of using QR codes for watermarking is that properties of the QR code structure include error correction and high data capacity. This paper proposes a QR code watermarking technique, and examines its robustness and security against common digital image attacks.

As we know that the world is been surrounded by the internet and interconnected to it and the different things or we can say the edge devices which helps us to connect to network and communicate to the different alternatives with the surroundings. In this paper we would be discussing about the different algorithms and their and disadvantages and how the advanced standard algorithm is been applied we has an great effect on cryptography and the different process carried out in the encryption and decryption process. In this paper the encryption and the decryption would be given in 128 bit format in hexadecimal, binary or any other format and the key expansion for getting the cipher text. in cryptography their are three classification for the expansion of the key which can be symmetric, asymmetric and the hash function in this paper we have discussed and the symmetric key is been given for both encryption and decryption process.as we know that we are using the 128 bit length which has 10 rounds and the initial round includes the state and the different transformation in the cryptograpy process which is the symmetric key expansion in which the same key is been applied to both encryption and decryption in binary, hexadecimal, etc. As it is lossless operation many applications can be derived using this algorithm as we are using symmetric key block cipher. We are limiting our paper with the 128 bit length of data in verilog language. For encryption and decryption the proposed paper describes the cryptograpy which would be having the fixed size. In this algorithm where we are using the symmetric key block cipher where the key would be given same with respect to encryption. Many applications it can be used as it is lossless operation. We limit our focus on 12b8 bit AES encryption and decryption where coded in VHDL coding. The proposed paper describes the private key cryptosystems which has a key with fixed size.

Even though, Massive MIMO (M-MIMO) technology offers good improvement in terms of performance and quality of communications between users and Base Stations (BS). This technology, still limited by a harmful constraint renowned Pilot Contamination (PC) problem. To beat this problem of PC, two approaches have been adapted as a medicine for this problem, which appears strongly in Multi-Cell M-MIMO systems. The first approach is based on assigning extra pilot sequences to different users, while the second approach obliges the reuse of the same set of pilots in different cells. This paper reviews, briefly, the problem of PC in M-MIMO systems. Thereafter, it analyzes and provides a comparison between two decontaminating strategies: the Soft Pilot Reuse (SPR) and the Pilot Assignment based on the Weighted Graph Coloring (WGC-PA), which are respectively based on the above-discussed approaches. The analysis presented in this paper is focused on the uplink phase (i.e reverse link).

The National Institute of Standards and Technology (NIST) started the standardization process for lightweight cryptography algorithms in 2018. By the end of the first round, 32 submissions have been selected as 2nd round candidates. NIST allowed designers of 2nd round submissions to provide small updates on both their specifications and implementation packages. In this work, we introduce a benchmarking framework for evaluating the performance of NIST Lightweight Cryptography (LWC) candidates on embedded platforms. We show the features and application of the framework and explain its design rationale. Moreover, we provide information on how we aim to present up-to-date performance figures throughout the NIST LWC competition. In this paper, we present an excerpt of our software benchmarking results regarding speed and memory requirements of selected ciphers. All up-to-date results, including benchmarking different test cases for multiple variants of each 2nd round algorithm on five different microcontrollers, are periodically published to a public website. While initially only the reference implementations were available, the ability of automatically testing the performance of the candidate algorithms on multiple platforms becomes especially relevant as more optimized implementations are developed. Finally, we show how the framework can be extended in different directions: support for more target platforms can be easily added, different kinds of algorithms can be tested, and other test metrics can be acquired. The focus of this paper should rather lay on the framework design and testing methodology than on the current results, especially for reference code.

In this paper, we deal with two validation techniques which may be adopted for improving the quality and ensuring the correctness of Distributed Information Systems. These two techniques are Formal Verification and Model Based Techniques. The first one consists in checking the correctness of a mathematical model used to describe the behavior of the considered system before its implementation. The second technique consists in deriving tests suites from the adopted model, executing them and finally deducing verdicts about the correctness of this system under test. In both cases, we need to tackle the explosion state challenge which corresponds to the fact of reaching a very large space of states and consuming a very long time during the validation process. To solve this problem we propose a set of appropriate techniques taken from the literature. We also identify a set of techniques which may be used for the optimization of the test component placement procedure.

Civil infrastructure inspection in hazardous areas such as underwater beams, bridge decks, etc., is a perilous task. In addition, other factors like labor intensity, time, etc. influence the inspection of infrastructures. Recent studies [11] represent that, an autonomous inspection of civil infrastructure can eradicate most of the problems stemming from manual inspection. In this paper, we address the problem of detecting cracks in the concrete surface. Most of the recent crack detection techniques use deep architecture. However, finding the exact location of crack efficiently has been a difficult problem recently. Therefore, a deep architecture is proposed in this paper, to identify the exact location of cracks. Our architecture labels each pixel as crack or non-crack, which eliminates the need for using any existing post-processing techniques in the current literature [5, 11]. Moreover, acquiring enough data for learning is another challenge in concrete defect detection. According to previous studies, only 10% of an image contains edge pixels (in our case defected areas) [31]. We proposed a robust data augmentation technique to alleviate the need for collecting more crack image samples. The experimental results show that, with our method, significant accuracy can be obtained with very less sample of data. Our proposed method also outperforms the existing methods of concrete crack classification.

A mixed method combining formal and auto-tuning approaches and aimed at maximizing efficiency of parallel programs (in terms of execution time) is proposed. The formal approach is based on algorithmic algebra and the usage of tools for automated design and synthesis of programs based on high-level algorithm specifications (schemes). Parallel software auto-tuning is the method of adjusting some structural parameters of a program to a target hardware platform to speed-up computation as much as possible. Previously, we have developed a framework intended to automate the generation of an auto-tuner from a program source code. However, auto-tuning for complex and nontrivial parallel systems is usually time-consuming due to empirical evaluation of huge amount of parameter values combinations of an initial parallel program in a target environment. In this paper, we extend our approach with statistical modeling and neural network algorithms that allow to reduce significantly the space of possible parameter combinations. The improvement consists in automatic training of a neural network model on results of “traditional” tuning cycles and the subsequent replacement of some auto-tuner calls with an evaluation from the statistical model. The method allows, particularly, transferring knowledge about the influence of parameters on program performance between “similar” (in terms of hardware architecture) computing environments for the same applications. The idea is to reuse a model trained on data from a similar environment. The use of the method is illustrated by an example of tuning a parallel sorting program which combines several sorting methods.

In this paper, we improve the theoretical background of the attacks on the DSA schemes of a previous paper, and we present some new more practical attacks.

Computer system security has related to security of software or the information processed. The underlying hardware used for information processing has considered to as trusted. The emerging attacks from Hardware Trojans (HTs) violate this root of trust. The attacks are in the form of malicious modification of electronic hardware at different stages; possess major security concern in the electronic industries. An adversary can mount HT in a net of the circuit, which has low transition probability. In this paper, the improvement of the transition probability by using test points and weighted random patterns is proposed. The improvement in the transition probability can accelerate the detection of HTs. This paper implements weighted random number generator techniques to improve the transition probability. This technique is evaluated on ISCAS 85’ benchmark circuit using PYTHON and SYNOPSYS TETRAMAX tool.

Each year automotive systems are becoming smarter thanks to their enhancement with sensing, actuation and computation features. The recent advancements in the field of autonomous driving have increased even more the complexity of the electronic components used to provide such services. ISO 26262 represents the natural response to the growing concerns in terms of the functional safety of electrical safety-related systems in this area. However, if the functional safety analysis of digital devices is quite a stable methodology, the same analysis for analog components is still in its infancy. This paper aims to explore the problem of fault analysis in analog circuits and how it can be integrated into the design processes with minimum effort. The methodology is based on analog language manipulation, analog fault instrumentation and automatic abstraction. An efficient and comprehensive flow for performing such an activity is proposed and applied to complex case studies.

In this paper, we survey state of the art in plagiarism detection techniques, called GPLAG. This technique can detect five popular plagiarism techniques, such as format alteration, identifier renaming, statement reordering, control replacement, and code insertion. The problem of this technique is that it becomes inefficient when PDG grows. To resolve a problem of time complexity, this paper proposes a way to perform program slicing first and PDG comparison later. Original program and plagiarized program are sliced respectively, then PDG of original program’s slice is compared with PDG of plagiarized program’s slice. Since program slicing reduces the size of PDG, time to compare PDGs can be reduced. We choose most used variables as slicing criterion, and we can maintain accuracy even after program slicing. By experiments we show that efficiency is enhanced and accuracy is also maintained.

Approximation-tolerant applications give a system designer the possibility to improve traditional design values by slightly decreasing the quality of result. Approximate computing methods introduced for various system layers present the right tools to exploit this potential. However, finding a suitable tuning for a set of methods during design or run time according to the constraints and the system state is tough. Therefore, this paper presents an approach that leads to a transparent view on different approximation methods. This transparent and abstract view can be exploited by tuning approaches to find suitable parameter settings for the current purpose. Furthermore, the presented approach takes multiple objectives and conventional methods, which influence traditional design values, into account. Besides this novel representation approach, this paper introduces a first tuning approach exploiting the presented approach.

Efficiently implementing a load balancing technique in graph traversal applications for GPUs is a critical task. It is a key feature of GPU applications as it can sensibly impact on the overall application performance. Different strategies have been proposed to deal with such an issue. Nevertheless, the efficiency of each of them strongly depends on the graph characteristics and no one is the best solution for any graph. This paper presents three different balancing techniques and how they have been implemented to fully exploit the GPU architecture. It also proposes a set of support strategies that can be modularly applied to the main balancing techniques to better address the graph characteristics. The paper presents an analysis and a comparison of the three techniques and support strategies with the best solutions at the state of the art over a large dataset of representative graphs. The analysis allows statically identifying, given graph characteristics and for each of the proposed techniques, the best combination of supports, and that such a solution is more efficient than the techniques at the state of the art.

Near-fault ground motions exhibiting forward directivity effects are critical for seismic design because they impose very large seismic demands on buildings due to their large-amplitude pulselike waveforms. The current challenge in seismic design codes is to recommend simple (easy-to-apply) yet proper rules to explain the near-fault forward directivity (NFFD) phenomenon for seismic demands. This effort is not new and has been the subject of research for over two decades. This paper contributes to these efforts and proposes an alternative set of rules to modify the elastic design spectrum of 475-year and 2475-year return periods for NFFD effects. The directivity rules discussed here are evolved from a relatively large number of probabilistic earthquake scenarios (probabilistic seismic hazard assessment, PSHA) that employ two recent directivity models. The paper first gives the background of the probabilistic earthquake scenarios and then introduces the proposed NFFD rules for seismic design codes. We conclude the paper by presenting some cases with the proposed rules to see how spectral amplitudes modify due to directivity.

Recent renewed interest in optimizing and analyzing floating-point programs has lead to a diverse array of new tools for numerical programs. These tools are often complementary, each focusing on a distinct aspect of numerical programming. Building reliable floating point applications typically requires addressing several of these aspects, which makes easy composition essential. This paper describes the composition of two recent floating-point tools: Herbie, which performs accuracy optimization, and Daisy, which performs accuracy verification. We find that the combination provides numerous benefits to users, such as being able to use Daisy to check whether Herbie’s unsound optimizations improved the worst-case roundoff error, as well as benefits to tool authors, including uncovering a number of bugs in both tools. The combination also allowed us to compare the different program rewriting techniques implemented by these tools for the first time. The paper lays out a road map for combining other floating-point tools and for surmounting common challenges.

In this paper, we investigate the DAP placement problem and propose solutions to reduce the distance between DAPs and smart meters. The DAP placement problem is formulated to two objectives, e.g., the average distance minimization and the maximum distance minimization. The concept of network partition is introduced in this paper and practical algorithms are developed to address the DAP placement problem. Extensive simulations are conducted based on a real suburban neighborhood topology. The simulation results verify that the proposed solutions are able to remarkably reduce the communication distance between DAPs and their associated smart meters.

With 3GPP 5G new radio (NR), proposals are already being discussed. Although participants offer various suggestions for the first 5G standardization, common ideas can already be identified. The purpose of the paper is to anticipate, in the context of massive multiple input multiple output (MIMO) systems, the main directions the standard would focus on; for example, a unified transmission scheme, multi-level channel state information (CSI), and non-linear precoding (NLP). The latter, an alternative to linear precoding employed in Long Term Evolution (LTE), is analyzed in detail in the paper.

Security is an ever-present consideration for applications and data in the cloud computing environment. As an important method of performing computations directly on encrypted data without any need of decryption and compromising privacy, homomorphic encryption is an increasingly popular topic of protecting the privacy of data in cloud security research. However, as high computational complexity of the homomorphic encryption, it will be a heavy workload for computing resources in the cloud computing paradigm. Motivated by this observation, this paper proposes a fast parallel scheme with DGHV algorithm based on CPU-4GPUs hybrid system. Our main contribution of this paper is to present a parallel processing stream scheme for large-scale data encryption based on CPU-4GPUs hybrid system as fast as possible. Particularly, the proposed method applies CPU-4GPUs parallel implementation to accelerating encryption operation with DGHV algorithm to reduce the time duration and provide a comparative performance study. We also make further efforts to design a pipeline architecture of processing stream in CPU-4GPUs hybrid system to accelerate encryption for DGHV algorithm. The experiment results show that our method gains more than 91% improvement (run time) and 70% improvement compared to the serial addition and multiplication operation with DGHV algorithm respectively.

Recently, NIST started the process of standardizing quantum-resistant public-key cryptographic algorithms. WalnutDSA, the subject of this paper, is one of the 20 proposed signature schemes that are being considered for standardization. Walnut relies on a one-way function called E-Multiplication, which has a rich algebraic structure. This paper shows that this structure can be exploited to launch several practical attacks against the Walnut cryptosystem. The attacks work very well in practice; it is possible to forge signatures and compute equivalent secret keys for the 128-bit and 256-bit security parameters submitted to NIST in less than a second and in less than a minute respectively.

This paper proposes an innovative single point cutting device that requires less maintenance than traditional micro-milling machines, being the cutting tools required simpler easier to develop. This satisfies the market demands on micro manufacturing, where devices must be more accurate and cheaper, able to create a diverse range of shapes and geometries with a high degree of accuracy. A stereo vision system has been implemented as an alternative to the current technologies in the market to locate the tool tip, and with this, make the proper corrections on the CNC machine. In this paper the development of such system is explored and discussed. Experimental results show the accuracy of the proposed system, given an error in the measurement of \({\pm }3\,{\upmu }\mathrm{m}\).

The vehicle industry manufacturer is showing an increased interest in remote diagnostics by improving customer relationship management and commercial interest. The special nature of construction machines fact that architectures and applications proposed for vehicular communication are not optimized for these types of vehicles. This paper proposes a new remote diagnostic architecture based on IEEE 802.11n for construction machines communication to the infrastructure on site. The mobile Internet is used to transmit collected data to the central monitoring application. We discuss the possible network selection algorithms, mobility and security protocols that can be implemented on the On Board Units (OBU). The proposed architecture is based on Host Identity Protocol (HIP). This protocol introduces a Host Identifier (HI) for naming the endpoints and use intensive cryptographic operation for security and mobility management. Due to their minimal computing capabilities, many single board computers used as OBU themselves suffer from applications which need intensive CPU usage. Thus, a performance analysis of HIP, implemented on single board computers, is proposed by the end of this paper.

In order to solve the security problem of ECC cryptosystem, the security deficiency of elliptic curve encryption is described firstly in this paper. Then, the method of OAEP (Optimal Asymmetric Encryption Padding) in the random oracle model is adopted to enhance the security of the existing ECC encryption system. An improved encryption padding scheme for ECC cryptosystem, namely EOAEP (ECC OAEP), is proposed and designed in this paper, Under the one-way assumption of encryption function, it has been proved that our scheme satisfies adaptive chosen ciphertext security by using the Game-Hopping technology according to the random oracle model.

In the industry, reconfigurable real-time systems are specified as a set of implementations and tasks with timing constraints. The reconfiguration allows to move from one implementation to another by adding/removing real-time tasks. Implementing those systems as threads generates a complex system code due to the large number of threads and the redundancy between the implementation sets. This paper shows an approach for software synthesis in reconfigurable uniprocessor real-time embedded systems. Starting from the specification to a program source code, this approach aims at minimizing the number of threads and the redundancy between the implementation sets while preserving the system feasibility. The proposed approach adopts Mixed Integer Linear Programming (MILP) techniques in the exploration phase in order to provide feasible and optimal task model. An optimal reconfigurable POSIX-based code of the system is manually generated as an output of this technique. An application to a case study and performance evaluation show the effectiveness of the proposed approach.

The rapid growth in Internet and communication technology has facilitated an escalation in the exchange of digital multimedia content. This has resulted in an increase in copyright infringement, which has led to a greater demand for more robust copyright protection mechanisms. Digital watermarking is a means of detecting ownership and illegal use of digital products. This paper presents an approach to watermarking images by embedding QR code information in a digital image. The notion of the proposed scheme is to capitalize on the error correction mechanism that is inherent in the QR code structure, in order to increase the robustness of the watermark. By employing the QR code’s error correction mechanism, watermark information contained within a watermarked image can potentially be decoded even if the image has been altered or distorted by an adversary. This paper studies the characteristics of the proposed scheme and presents experiment results examining the robustness and security of the QR code watermarking approach.

Coding standards and guidance for secure programming call for sensitive data to be “sanitized” before being de-allocated. This paper considers what this really means in technical terms, why it is actually rather difficult to achieve, and how such a requirement can be realistically implemented and verified, concentrating on the facilities offered by Ada and SPARK. The paper closes with a proposed policy and coding standard that can be applied and adapted to other projects.

In this paper we propose a stopwatch automata-based model of a modular computer system operation. This model provides an ability to perform schedulability analysis for a wide class of modular computer systems. It is formally proven that the model satisfies a set of correctness requirements. It is also proven that all the traces, generated by the model interpretation, are equivalent for schedulability analysis purposes. The traces equivalence allows to use any trace for analysis and therefore the proposed approach is much more efficient than Model Checking, especially for parallel systems with many simultaneous events. The software implementation of the proposed approach is also presented in the paper.

This paper presents the results obtained by the authors on applying an integrated approach to solving geoseismics, astrophysics, and plasma physics problems on high-performance computers. The concept of the integrated approach in the context of mathematical modeling of physical processes is understood as constructing a physico-mathematical model of a phenomenon, a numerical method, a parallel algorithm and its software implementation with the efficient use of a supercomputer architecture. With this approach, it becomes relevant to compare not only the methods of solving a problem but, also, physical and mathematical statements of a problem aimed at creating the most effective implementation of a chosen computing architecture. The scalability of algorithms is investigated using the multi-agent system AGNES simulating the behavior of computing nodes based on the current state of computer equipment characteristics. In addition, special attention in this paper is given to the energy efficiency of algorithms.

Due to high complexity on matching computation, real-time object tracking is generally a very challenging task for practical applications. This paper proposes a new algorithm for moving object tracking, which improves the traditional KLT algorithm by using the motion information for feature points selection to avoid the irrelevant feature points residing in the background area. Moreover, this paper designs the hardware architecture of the FPGA part to accelerate the computation by optimizing the inherent parallelism of the algorithm. The proposed algorithm is able to significantly reduce the computation time. Experimental results show that our algorithm implemented in an FPGA-SoC (Zynq 7020, 667 MHz) requires only 0.030 s to handle a VGA resolution frame, which is suitable for real-time tracking. This achieves up to \(30{\times }\) performance improvement compared with the desktop PC (i3, 3.4 GHz), or \(370{\times }\) compared with the ARM (Cortex-A8, 1 GHz). The experiment also shows that our approach consumes less energy significantly than PC and ARM for the same workload, which indicates that it is suitable for energy-critical system.

This paper presents the development of PLC-based systems for data acquisition and supervisory control of environment-friendly energy-saving complex high-tech technologies. The functional structure and main components of PLC-based SCADA-systems for environment-friendly energy-saving technological processes are given. The examples of SCADA applications in design of PLC-based systems for monitoring and automatic control of (a) ecopyrogenesis (EPG) and (b) thermoacoustic technological processes are presented. Paper considers the criteria of energy and economic efficiency of the EPG technological process. The functional structures, software and hardware implementation as well as multi-level human-machine interfaces of the developed PLC-based systems for data acquisition and supervisory control are given. Considerable attention is given to particular qualities of computing of ecopyrogenesis and thermoacoustic processes technological parameters by the proposed SCADA-systems. The developed PLC-based SCADA-systems provide: significant increasing of energy and economic efficiency criteria of the EPG and TAD complexes, high precision control of both technological processes, monitoring of current technological parameters, using the indirect methods for parameters measuring and identifying, and automatic control with high quality indicators and optimal parameters.

This paper presents a genetic programming (GP) approach enhanced with a local search heuristic (GP-LS) to emulate the Doherty 7 W @ 2.11 GHz Radio Frequency (RF) Power Amplifier (PA) conversion curves. GP has been shown to be a powerful modeling tool, but can be compromised by slow convergence and computational cost. The proposal is to combine the explorative search of standard GP, which build the syntax of the solution, with numerical methods that perform an exploitative and greedy local optimization of the evolved structures. The results are compared with traditional modeling techniques, particularly the memory polynomial model (MPM). The main contribution of the paper is the design, comparison and hardware emulation of GP-LS for FPGA real applications. The experimental results show that GP-LS can outperform standard MPM, and suggest a promising new direction of future work on digital pre-distortion (DPD) that requires complex behavioral models.

This paper is focused on finding the efficient path generating algorithms. These algorithms can take part in the path planning process, which is the last stage in model processing for 3D printing. The paper provides the comparative analysis of the five implemented path generating algorithms, which are based on four strategies: ZigZag strategy, Contour strategy, Spiral Strategy, and Fractal strategy. The analysis is based on the results of experiments made with the designed and implemented experimentation system. The system allows carrying out two types of experiments: simulation experiments and physical one. The simulation experiment is performed with the programming application written in C#. The physical experiments utilized FDM technology for 3D printing. Basing on the obtained results, we can conclude that the algorithm based on the ZigZag strategy seems to be better than the algorithms based on other approaches.