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In the 3D integrated circuit package industry, the remelting of solder joints during repeated stacking processes can cause electrical failure and low bonding strength. Transient liquid phase sintering (TLPS) bonding based on forming full intermetallic compounds (IMCs) in the solder joint to increase the remelting point has emerged as a potential solution to this issue. Here, pressureless TLPS Cu-Cu bonding was conducted with Sn-3.0Ag-0.5Cu solder powders and various Ag flake powder content (15 wt.%, 30 wt.%, 45 wt.%, and 60 wt.%). The TLPS paste was screen-printed and the bonding process was conducted at 255°C for 2 h in an air atmosphere without bonding pressure. Additionally, this study investigated the microstructural evolution and fracture modes of the TLPS joints after the shear tests were investigated. High-temperature storage tests were conducted at 300°C for 24 h, 48 h, and 96 h, and a shear test was then performed to evaluate bonding strength. A differential scanning calorimetry analysis of the TLPS paste was conducted to investigate the thermal behavior of the paste during the bonding process. No residual solder was found in TLPS joints with an Ag flake content above 45 wt.% The highest bonding strength in a TLPS joint with full IMC layers was 27.3 MPa, representing an approximately 9% decrease after 96 h of high-temperature storage test. TLPS bonding with an optimal composition was resistant to the remelting of solder joints due to the full IMC layers, i.e., it represents a reliable interconnection method for 3D stacking. [ABSTRACT FROM AUTHOR]

Low-temperature soldering constitutes a promising solution in interconnect technology with the increasing trend of heat-sensitive materials in integrated circuit packaging. Experimental work was carried out to investigate the effect of electroless Ni/electroless Pd/immersion gold (ENEPIG) layer thicknesses on Sn-Bi-Ag solder joint integrity during extended reflow at peak temperatures as low as 175°C. Optimizations are proposed to obtain reliable solder joints through analysis of interfacial microstructure with the resulting joint integrity under extended reflow time. A thin Ni(P) layer with thin Pd led to diffusion of Cu onto the interface resulting in Ni3Sn4 intermetallic compound (IMC) spalling with the formation of thin interfacial (Ni,Cu)3Sn4 IMCs which enhance the robustness of the solder after extended reflow, while thick Ni(P) with thin Pd resulted in weakened solder joints with reflow time due to thick interfacial Ni3Sn4 IMCs with the entrapped brittle Bi-phase. With a suitable thin Ni(P), the Pd thickness has to be optimized to prevent excessive Ni-P consumption and early Cu outward diffusion to enhance the solder joint during extended reflow. Based on these findings, suitable Ni(P) and Pd thicknesses of ENEPIG are recommended for the formation of robust low-temperature solder joints. [ABSTRACT FROM AUTHOR]

This study investigates fluid-structure interaction (FSI) analysis of stacked chip in the encapsulation of molded underfill packaging using ANSYS Coupling Work bench with fluid and structural solvers. During encapsulation, FSI analysis is applied to a molded package with different layouts, namely cases 1-4 of stacked chip. An even ratio of inlet and outlet gate pressures is used to produce a regular melt front advancement. An experimental setup is fabricated to validate the simulation results in the FSI study. A digital camera is used to capture the melt front advancement and structural deformation. The interaction between structures (silicon chip) and epoxy molding compound (EMC) is displayed in the displacement profile. Maximum deformation is evaluated during the final stage of filling. The silicon die experiences von Mises stresses, which are monitored to observe the risk of die cracking. The results of this study showed that, the EMC flow front advancement was the fastest in case 4. The pressure distribution of each case was nearly identical, and the maximum von Mises stress was distributed unevenly at the middle of the stacked chip. The proposed analysis can serve as a reference and guide in designing and improving 3D integration packages in industry. [ABSTRACT FROM AUTHOR]

Purpose: The pressure on brand firms in the electronics industry to improve the labor conditions of their workers in their global production networks is increasing. Given the significance of mitigating the impacts of production on labor, this study used the new development method of social life cycle impact assessment (SLCIA) for conducting labor impact assessment. An illustrative example in an integrated circuit (IC) packaging company is presented to demonstrate the assessment of the impacts and the identification of the potential for improvement of labor practices among three factories. Methods: SLCIA method was proposed based on the UNEP/SETAC Guidelines that were reviewed in our previous work, Part 1 (in a previous article): Methodology. The proposed method was used to assess the impacts of operations on labor in the three factories of an IC packaging company. Nineteen indicators of labor-stakeholders were used to collect data from factories and organizations in 2012. The obtained values from these three factories were translated into social impact scores that ranged from 1 to 5. The score of each indicator was multiplied by the weights of each indicator, and a final score of labor situations was generated to identify the hotspots of labor impacts and to identify the factory with better labor performance. Results and discussion: The main goal of this study is to demonstrate the effectiveness of our proposed SLCIA method in assessing the labor impacts in the electronics industry. Among three factories of IC packaging, factory C was ranked as having the lowest social impact on labor with a higher performance, followed by factories B and A. In addition, the results show that four indicators, 'lacking labor union,' 'did not hire a sufficient number of disabled employees,' 'overtime work that exceeded the legal limit,' and 'excessive number of dispatched workers,' were recognized as the main social impacts on labor in IC packaging production. Conclusions: The SLCA technique was used to assess the impacts of the production processes of three IC packaging factories on the labor conditions of their factory workers. The proposed method shed light on the significant impacts of such processes. The proposed model demonstrated its potential advantage by systematically and effectively identifying the labor impact hotspots, which could assist managers in devising strategies that could improve the labor situations within their organizations. [ABSTRACT FROM AUTHOR]

This paper considers electrochemical tin deposition for producing contact elements in integrated circuit packaging. We examine the effect of organic additives to sulfate electrolytes on the growth of local vertical structures, with the aim of suppressing lateral growth of the deposit. [ABSTRACT FROM AUTHOR]

In this paper, we present a complete 700-2,600 MHz RF SiP module for micro base station. This RF SiP design integrates transmitter, receiver, feedback module, ADC/DAC and CLK module. The module consists of two multi-layer organic substrates that are vertically stacked using BGA interconnections. With the integration of 33 chips and about 600 passive components, this RF SiP module retains small form factor and measures 5.25 cm × 5.25 cm × 0.7 cm. The RF input signal transmission path insertion loss is less than 0.34 dB and the return loss is less than −14 dB at 2.6 GHz. Full load thermal simulation result indicates that each chip junction temperature is below 100 °C. We summarize the RF SiP module design, assembly and simulated thermal characteristics. The proposed RF SiP can generally be characterized by small size, low cost and short development cycle. [ABSTRACT FROM AUTHOR]

Finite element method and Garofalo-Arrheninus creep model were combined and used to evaluate the reliability of different lead-free solder joints (SnAgCu, SnAg, SnSb and SnZn) and SnPb solder joints in chip scale package (CSP) 14 × 14 device under thermal cyclic loading. The results show that von Mises stress and equivalent creep strain in each of the four lead-free solder joints and SnPb solder joints were strongly different, increasing in the order SnPb < SnAg < SnSb < SnZn < SnAgCu. It is found that maximum stress-strain concentrates on the top-surface of corner solder joints in the CSP device for all solder joints, and SnAgCu solder joints shows the highest fatigue life among those five kinds of solder joints. [ABSTRACT FROM AUTHOR]

Cu-to-Cu bonding to connect through-silicon vias in three-dimensional integrated-circuit packaging is the most important interconnection technology in the next-generation semiconductor industry. Soldering is an economic and fast process in comparison with diffusion bonding methods. Ga has high solubility of up to 20 at.% in the Cu-rich face-centered cubic (FCC) phase and high mobility at moderate temperatures. In this work, an attempt has been made to evaluate Ga-based Cu-to-Cu interconnection by transient liquid-phase (TLP) bonding. The Cu/Ga interfacial reactions at temperatures ranging from 160°C to 300°C were examined. For reactions at temperatures lower than 240°C, the reaction path is Cu/ γ-CuGa/ θ-CuGa/liquid, where the γ-CuGa and θ-CuGa phases are thin planar and thick scalloped layers, respectively, while for the reactions at 280°C and 300°C, the scalloped γ-CuGa phase is the only reaction product. The phase transformation kinetics, reaction mechanisms, and microstructural evolution in the Cu/Ga couples are elaborated. In addition, reactions of Cu/Ga/Cu sandwich couples at 160°C were investigated. The original Cu/liquid/Cu couples isothermally transformed to Cu/ γ-CuGa/ θ-CuGa/ γ-CuGa/Cu couples as the reaction progressed. However, cracks were observed in the θ-CuGa phase regions after metallographic processing. The brittle θ-CuGa phase is undesirable for Ga-based TLP bonding. [ABSTRACT FROM AUTHOR]

This study investigated electromigration (EM) behaviors of Pb-free microbumps in three-dimensional integrated circuit (3D IC) packaging under electrical current stressing from 1 × 10 A/cm to 1 × 10 A/cm at ambient temperature of 150°C. EM-induced fast under bump metallization consumption at the cathode of the microbumps was observed when the current density was higher than 8 × 10 A/cm, whereas no EM-induced damage of the microbumps was found after 14,416 h when the current density was below 1.5 × 10 A/cm. We propose that the different EM behaviors of the microbumps were mainly due to the effect of back stress. The critical microbump height to trigger EM for different current densities is discussed, and the resistance evolution of samples during current stressing was found to be correlated with the microstructure of the samples. When the resistance was stable through the whole test period, microscopic inspection of the 3D IC samples indicated that the whole microbumps were transformed to intermetallic compounds without significant EM-induced damage. However, the resistance evolution of some misaligned microbumps exhibited a feature of an early spike along with a huge resistance fluctuation during current stressing. When the resistance abruptly increased after lengthy stressing, EM-induced void formation was observed at the cathode side of the Al trace. [ABSTRACT FROM AUTHOR]

The lead trim-and-form process is important in the manufacturing of programmable logic devices, microprocessors, and memories. Normally, inspection of a chip package is performed in a lead inspection machine after the lead forming process to detect defects on the leads. One such defect is the lead intermetallic compound (IMC) crack, exhibiting itself as plating crack. In this study, IMC crack of package leads, which causes loose connection between the copper lead and the tin plating, was analyzed using the finite-element method. The simulation results were verified by matching the simulated and actual formed lead profile. Simulation results showed a strong correlation between IMC crack after forming and aging and high residual tensile strain induced during lead forming. A proposal was made to resolve the crack issue by performing design of experiment (DOE) to reduce the residual tensile strain of the lead upon forming. Three optimization parameters were chosen, namely the forming angle, the shank angle, and the pre-forming angle. It is shown that, with the optimized parameter setting, a reduction of the residual strain can be achieved, thus minimizing the risk of IMC crack. [ABSTRACT FROM AUTHOR]

A materials investigation of Au wire bonds to Al pads revealed the evolution of a multiphase system whose terminal phases depended on the composition of the Au wire. Scanning transmission electron microscopy/energy-dispersive spectroscopy and electron diffraction data are presented for Au/Al wire bonds using both Pd-doped, 99% pure Au wire (2N) and 99.99% pure Au wire (4N) in the as-formed state, upon completion of overmold operations, and after reflow and aging. The reacted interfaces of both the 2N and 4N bonds were found to take on a bilayer intermetallic compound (IMC) microstructure that persisted with aging and phase changes; it is the interface of this bilayer that is believed to be susceptible to mechanical degradation. Pd was found to accumulate in the IMC near the Au/IMC interface for 2N wire bonds and appears to lead to a phase evolution different from that for 4N wire that may be responsible for enhanced reliability of the 2N wire bond with high-temperature aging. [ABSTRACT FROM AUTHOR]

A new wafer-level chip-scale package process for high-performance, low-cost packaging has been developed based on passivation with low dielectric constant. This process is simpler and shorter when using permanent photosensitive benzocyclobutene (BCB) compared with the conventional process. However, cracks nucleating on the BCB cause serious reliability problems. The major reasons for cracking of the BCB layer seem to be both thermal stress and a shortage of BCB cross-linking agent (cyclobutene). The stress was reduced by optimizing the thickness of the BCB layer and the underlying stress buffer layer. The BCB cracking resistance was improved by creating more cross-linking agent at the final curing process through modification of the photolithography processes. [ABSTRACT FROM AUTHOR]