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Conventional modular multilevel converters (MMCs) are promising converters for high‐voltage high‐power applications. Unlike DC–AC conversion, DC–DC conversion of MMCs suffers from unbalanced capacitor voltages due to the energy drift problem. In this study, a new modular DC–DC converter is proposed, which consists of front‐end half‐bridge MMC with half‐bridge submodules followed by full‐bridge MMC with full‐bridge submodules. The proposed modular multilevel DC–DC converter can be used effectively for connecting two different DC voltage levels in high‐/medium‐voltage DC grids. The proposed architecture provides successful DC–DC conversion with balanced capacitor voltages throughout the arm interchange concept. It also provides a high conversion ratio, bidirectional power flow, low losses, low current stresses, reduced number of submodules, and DC fault blocking capability. Detailed illustration, operational concept, and design of the proposed architecture with the arm interchange concept are presented. Simulation results for a high‐voltage high‐power DC–DC converter with the suggested approach are presented to demonstrate the system performance during different normal as well as abnormal operating conditions. Finally, a scaled‐down prototype has been implemented for validation. The extracted simulation and experimental results elucidate the presented claims. [ABSTRACT FROM AUTHOR]

This paper proposes a new high-voltage pulse generator (PG) fed from a low-voltage DC supply Vs, which charges one arm of N series-connected full-bridge (FB) modular multilevel converter (MMC) sub-module (SM) capacitors sequentially, through a resistive-inductive branch. By utilising FB-SMs, the proposed PG is able to generate bipolar rectangular pulses of peak NVs and unipolar rectangular pulses of either polarity, at high repetition rates. Asymmetrical pulses are also possible. The proposed topology is assessed via simulation and scaled-down experimentation, which establish the viability of the topology for water treatment applications. [ABSTRACT FROM AUTHOR]

In this study, a cost‐effective HVDC shunt tap with low‐number of relatively low‐voltage semiconductor devices and small‐sized passive components is proposed. The proposed architecture is based on employing three single‐phase half‐bridge Modular Multilevel Converters (MMCs), where the DC sides of MMCs are connected in series across the total DC‐link voltage. The MMCs are adopted instead of conventional Two‐Level Voltage Source Converters (2L‐VSCs) to avoid the complications of series connection of Insulated Gate Bipolar Transistors (IGBTs). The involved MMCs in the suggested architecture are operated with the conventional 2L modulation, which results in insignificant arm inductors and Sub‐Modules (SMs) capacitances (in range of µH and µF, respectively). This, in turn, affects positively the converter cost and footprint. Each arm of the involved MMCs can be considered as a high‐voltage valve of a 2L‐VSC. To maintain the balance of SMs capacitors, each arm of the involved (N + 1)‐level MMC has an extra SM (a balancing SM) to select N out of N + 1 SMs during the turn‐off condition. The operational concept, design, and assessment of the proposed architecture are presented in this study. Simulation results are provided for substantiation of the proposed concept. Finally, a scaled down single‐phase prototype is used for experimental validation. [ABSTRACT FROM AUTHOR]

The half‐bridge modular multilevel converter (HB‐MMC) is one of the most promising topologies for high‐voltage direct current (HVDC) systems. Unlike full‐bridge MMC (FB‐MMC) and clamp double sub‐module MMC (CDSM‐MMC), HB‐MMCs are defenceless against DC side faults. Different types of DC circuit breakers (DC CBs) assisted with arrester banks/damping resistors such as solid‐state CB and hybrid DC CBs can be used to interrupt the DC fault current. Arrester banks are used to protect against overvoltage after interrupting the fault current and in turn to demagnetise the circuit inductors. The main disadvantage of the arresters is that they forcibly break apart when they are overloaded. In this study, an arrester‐less fault current limiter is proposed for HB‐MMC configuration, which provides an opposing voltage during the DC side fault. This is achieved by inserting external pre‐charged capacitors in the DC current path during the fault. The selection of these external capacitors, their suitable initial voltages, and their charging stations are also presented in this study. A comparison between the proposed scheme and the CDSM‐MMC has been held as well. The proposed protection scheme is assessed using a simulation study for a point‐to‐point nine‐level HB‐MMC‐based HVDC system. [ABSTRACT FROM AUTHOR]

This study proposes a new architecture of flywheel energy storage system (FESS) which can be implemented at generating unit (GU) level (e.g. wind turbine) or scaled up for application in grid‐side converter (GSC) stations of a multi‐terminal direct current (MTDC) system. The proposed architecture suppresses DC voltage leaps under grid faults, and performs power levelling duty at grid connection points. When implemented at GU level, the proposed FESS features a doubly‐fed induction machine (DFIM) – the flywheel machine – where its six stator winding terminals are connected in series between the grid and the GSC. The flywheel converter is of partial power rating, and is connected to the DFIM rotor. When employed at an MTDC GSC station, several submodules are connected to build an FESS station. The study proposes the control concept and the general topology of the FESS station. The performance parameters of the system are tested under normal and abnormal operating conditions. Results and analyses indicate smooth dynamic operation, the economic advantage and the improved fault ride‐through capability because of the proposed system. [ABSTRACT FROM AUTHOR]