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In this paper, we propose an energy efficient approximate multiplier design obtained by truncating the input operands. In the structure, the n-bit multiplication operation is transformed to a smaller bit length multiplication plus some add and shift operations. The simple calculation core makes the multiplier a scalable yet low power structure. Also, we suggest an output quality-tunable multiplier providing ability to change the output quality during the multiplication operation. The characteristics of the proposed multiplier are compared with those of the exact and some other approximate multipliers in a 45 nm technology. The comparison reveals an average improvement of 89.2% (74.9%) in terms of the energy (area) compared to that of the exact multiplier. The utility of the proposed multiplier in a JPEG encoder application is also investigated. The results reveal that the Peak Signal to Noise Ratio (PSNR) reduction is at most 0.15 dB compared to that of the exact one. [ABSTRACT FROM AUTHOR]