Search

Although microfluidic paper-based analytical devices (μPADs) get a lot of attention in the scientific literature, they rarely reach the level of commercialization. One possible reason for this is a lack of application of machine learning techniques supporting the design, optimization and fabrication of such devices. This work demonstrates the potential of two chemometric techniques including design of experiments (DoE) and digital image processing to support the production of μPADs. On the example of a simple colorimetric assay for isoniazid relying on the protonation equilibrium of methyl orange, the experimental conditions were optimized using a D-optimal design (DO) and the impact of multiple factors on the μPAD response was investigated. In addition, this work demonstrates the impact of automatic image processing on accelerating color value analysis and on minimizing errors caused by manual detection area selection. The employed algorithm is based on morphological recognition and allows the analysis of RGB (red, green, and blue) values in a repeatable way. In our belief, DoE and digital image processing methodologies are keys to overcome some of the remaining weaknesses in μPAD development to facilitate their future market entry.

This registration contain information about my research article "A novel deep learning method for recognizing texts printed with multiple different printing methods" and its extended/underlying data which are required by publisher (F1000Research).

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

Editor-in-Chief Harry Levinson introduces a new set of guidelines for papers related to computational lithography.

Lately, Deep Learning has indicated its capacity by adequately tackling complex learning issues which were not possible previously. Specifically, Convolutional Neural Networks are most generally utilized and have indicated their viability in image detection and recognition problems. Convolutional Neural Networks(CNN) can be used to perform different kinds of tasks. However, to recognize even a single image, billions of calculations are required. For example, ResNet 50 takes 8 billion calculations just to figure out what's in a single image. So we need to find out ways to be able to run that superfast and that's why we need hardware accelerators. In this paper the basic information about Convolutional Neural Networks is provided along with the key operations involved and the brief idea about Field Programmable Gate Arrays(FPGA) is given which enable them to be used for accelerating the inference process of Convolutional Neural Networks. Various techniques which were employed previously for accelerating the Convolutional Neural Networks are discussed. We are focussing on designing a energy efficient Field Programmable Gate Arrays accelerator for accelerating the inference process of Convolutional Neural Networks with reduced latency and increased throughput.

Being able to learn from complex data with phase information is imperative for many signal processing applications. Today’s real-valued deep neural networks (DNNs) have shown efficiency in latent information analysis but fall short when applied to the complex domain. Deep complex networks (DCN), in contrast, can learn from complex data, but have high computational costs; therefore, they cannot satisfy the instant decision-making requirements of many deployable systems dealing with short observations or short signal bursts. Recent, Binarized Complex Neural Network (BCNN), which integrates DCNs with binarized neural networks (BNN), shows great potential in classifying complex data in real-time. In this paper, we propose a structural pruning based accelerator of BCNN, which is able to provide more than 5000 frames/s inference throughput on edge devices. The high performance comes from both the algorithm and hardware sides. On the algorithm side, we conduct structural pruning to the original BCNN models and obtain 20 × pruning rates with negligible accuracy loss; on the hardware side, we propose a novel 2D convolution operation accelerator for the binary complex neural network. Experimental results show that the proposed design works with over 90% utilization and is able to achieve the inference throughput of 5882 frames/s and 4938 frames/s for complex NIN-Net and ResNet-18 using CIFAR-10 dataset and Alveo U280 Board.

We propose a coding scheme for low-latency distributed inference at the network edge that combines a rateless code with an irregular-repetition code. The rateless code provides robustness against straggling servers and serves the purpose of reducing the computation latency, while the irregular-repetition code provides spatial diversity to reduce the communication latency. We show that the proposed scheme yields significantly lower latency than a scheme based on maximum distance separable codes recently proposed by Zhang and Simeone.

A summary of contributions made by significant papers from the first 25 years of the Field-Programmable Logic and Applications conference (FPL) is presented. The 27 papers chosen represent those which have most strongly influenced theory and practice in the field.

The work presented in this paper forms part of a literature review conducted during a study on error detection and correction systems. The research formed the foundation of understanding, touching on space radiation, glitches and upsets, geomagnetism, error detection and correction (EDAC) schemes, and implementing EDAC systems. EDAC systems have been around for quite some time, and certain EDAC schemes have been implemented and tested extensively. However, this work is a more focused study on understanding and finding the best-suited EDAC solution for nanosatellites in low earth orbits (LEO).

Predictions have a long and rich history in online optimization research, with applications ranging from video streaming to electrical vehicle charging. Traditionally, different algorithms are evaluated on their performance given access to the same type of predictions. However, motivated by the problem of bandwidth cost minimization in large distributed systems, we consider the benefits of using different types of predictions. We show that the two different types of predictors we consider have complimentary strengths and weaknesses. Specifically, we show that one type of predictor has strong average-case performance but weak worst-case performance, while the other has weak average-case performance but strong worst-case performance. By using a learning-augmented meta-algorithm, we demonstrate that it is possible to exploit both types of predictors for strong performance in all scenarios.

The Oblivious Relay serves users without a need to know the users error correcting codes. We extend the oblivious relay concept to channels with interference which is known to the transmitter but not to the receiver. Our system uses structured modulation and coding based on lattices. We show that when the interference is known non-causally, it's influence can be overcome wholly and that in simpler causal schemes the performance is usually within the shaping loss of 0.254 bits/channel use from the optimal performance attainable with large lattices.

With the increasing popularity of optimization algorithms in electromagnetic engineering, it is clear that mixed-variable design problems prevail. This paper shows that the Cross-Entropy (CE) optimization method is intrinsically versatile to handle these and other types of problems. We provide implementation details of two antenna examples optimized by the CE method to demonstrate its elegance and efficiency.

While there are several frameworks for CNN inference on mobile GPUs, they do not achieve real-time processing for the most of the CNNs that aim at reasonable accuracy since they all employ kernel-by-kernel execution model and do not effectively support INT8 quantization yet. In this paper, we reveal that mobile GPUs suffer from large kernel launch overhead unlike server GPUs, and then propose an on-device deep learning inference framework that can achieve real-time inference of CNNs on mobile GPUs by removing kernel launch overhead and by effectively exploiting INT8 quantization. We have evaluated the proposed framework with a state-of-the-art CNN based face detector (RetinaFace), and observed up to 2.01X of speedup compared to ARM Compute Library (ACL) on a commodity smartphone.

Value Prediction was proposed to speculatively break true data dependencies, thereby allowing Out of Order (OOO) processors to achieve higher instruction level parallelism (ILP) and gain performance. State-of-the-art value predictors try to maximize the number of instructions that can be value predicted, with the belief that a higher coverage will unlock more ILP and increase performance. Unfortunately, this comes at increased complexity with implementations that require multiple different types of value predictors working in tandem, incurring substantial area and power cost. In this paper we motivate towards lower coverage, but focused, value prediction. Instead of aggressively increasing the coverage of value prediction, at the cost of higher area and power, we motivate refocusing value prediction as a mechanism to achieve an early execution of instructions that frequently create performance bottlenecks in the OOO processor. Since we do not aim for high coverage, our implementation is light-weight, needing just 1.2 KB of storage. Simulation results on 60 diverse workloads show that we deliver 3.3% performance gain over a baseline similar to the Intel Skylake processor. This performance gain increases substantially to 8.6% when we simulate a futuristic up-scaled version of Skylake. In contrast, for the same storage, state-of-the-art value predictors deliver a much lower speedup of 1.7% and 4.7% respectively. Notably, our proposal is similar to these predictors in performance, even when they are given nearly eight times the storage and have 60% more prediction coverage than our solution.

In this paper, we introduce the optimal design methods of 3D NAND nvCIM [1], and then address the read disturb reliability issue. In recent years CIM [2] is widely considered as a promising solution to accelerate the DNN inference hardware. Theoretically, nvCIM can drastically reduce the power consumption by data movement because of no need to move the weights during computation. 3D NAND has the advantage of extremely low Icell (~nA), while the large ON/OFF ratio provides the capability to sum >10’000 cells together to improve the performance bandwidth and energy efficiency. We think that 3D NAND nvCIM has the potential to serve as the inference accelerator for the high-density fully- connected (FC) network which often requires high-bandwidth inputs. The read disturb property is studied. It is suggested that the "on-the-fly" calibration technique can well maintain the inference accuracy for 10-year usage.

With the introduction of Virtual Network Functions (VNF), network processing is no longer done solely on special purpose hardware. Instead, deploying network functions on commodity servers increases flexibility and has been proven effective for many network applications. However, new industrial applications and the Internet of Things (IoT) call for event-based systems and midleware that can deliver ultra-low and predictable latency, which present a challenge for the packet processing infrastructure they are deployed on. In this industry experience paper, we take a hands-on look on the performance of network functions on commodity servers to determine the feasibility of using them in existing and future latency-critical event-based applications. We identify sources of significant latency (delays in packet processing and forwarding) and jitter (variation in latency) and we propose application- and system-level improvements for removing or keeping them within required limits. Our results show that network functions that are highly optimized for throughput perform sub-optimally under the very different requirements set by latency-critical applications, compared to latency-optimized versions that have up to 9.8X lower latency. We also show that hardware-aware, system-level configurations, such as disabling frequency scaling technologies, greatly reduce jitter by up 2.4X and lead to more predictable latency.

“Writing on dirty paper” refers to the communication problem over a channel with both noise and interference, where the interference is known to the encoder non-causally and unknown to the decoder. This problem is regarded as a basic building block in both the single-user and multiuser communications, and it has been extensively investigated by Costa and other researchers. However, little is known in the case that the encoder can have access to feedback from the decoder. In this paper, we study the dirty-paper coding problem for feedback Gaussian channels without or with memory. We provide the most power efficient coding schemes for this problem, i.e., the schemes achieve lossless interference cancelation. These schemes are based on the Kalman filtering algorithm, extend the Schalkwijk-Kailath feedback codes, have low complexity and a doubly exponential reliability function, and reveal the interconnections among information, control, and estimation over dirty-paper channels with feedback. This research may be found useful to, for example, powerconstrained sensor network communication.

Video detection and classification constantly involve high dimensional data that requires a deep neural network (DNN) with huge number of parameters. It is thereby quite challenging to develop a DNN video comprehension at terminal devices. In this paper, we introduce a deeply tensor compressed video comprehension neural network called DEEPEYE for inference at terminal devices. Instead of building a Long Short-Term Memory (LSTM) network directly from raw video data, we build a LSTM-based spatio-temporal model from tensorized time-series features for object detection and action recognition. Moreover, a deep compression is achieved by tensor decomposition and trained quantization of the time-series feature-based spatio-temporal model. We have implemented DEEPEYE on an ARM-core based IOT board with only 2.4W power consumption. Using the video datasets MOMENTS and UCF11 as benchmarks, DEEPEYE achieves a 228.1× model compression with only 0.47% mAP deduction; as well as 15k× parameter reduction yet 16.27% accuracy improvement.

Robustness is a key requirement for deploying a machine learning (ML) based solution. When a solution involves a ML model whose robustness is not guaranteed, ensuring robustness of the solution might rely on continuous checking of the ML model for its validity after the solution is deployed in production. Using wafer image classification as an example, this paper introduces tensor-based methods that help improve robustness of a neural-network-based classification approach and facilitate its deployment. Experiment results based on data from a commercial product line are presented to explain the key ideas behind the tensor-based methods.

Due to continued technology scaling, electromigration (EM) signoff has become increasingly difficult, mainly due to the use of inaccurate methods for EM assessment, such as the empirical Black's model. In this paper, we review the state of the art for EM verification in on-die power/ground grids, with emphasis on a recent finite-difference based approach for power grid EM checking using physics-based models. The resulting model allows the EM damage across the power grid to be simulated based on a Linear Time Invariant (LTI) system formulation. The model also handles early failures and accounts for their impact on the grid lifetime. Our results, for a number of IBM power grid benchmarks, confirm that existing approaches for EM checking can be highly inaccurate. The lifetimes found using our physics-based approach are on average about 2X, or more, those based on the existing approaches, showing that existing EM design guidelines are overly pessimistic. The method is also quite fast, with a runtime of about 8 minutes for a 4M node grid, and so it is suitable for large circuits.

In the existing Leave Automation Record, every College Department follows manual procedure in which collage faculty enters information in a record book. At the end of each month, Administration Department calculates leave s of every faculty which is a more time taking process and there are chances of losing data or errors in the records. This module is a single leave automation that is critical for HR tasks and keeps the record of virtual information regarding leaves. It intelligently adapts to HR policy of the automation and allows employees and their line managers to manage leaves and replacements if required . In this module, Head of Department HOD will have permissions to look after data of every faculty member of their department. HOD can approve leave through this application and can view leave information of every individual. This system can be used in a college to reduce processing work load. This project's main idea is to develop an online centralized application connected to database which will maintain faculty leaves and their replacements if needed . Proposed System will reduce paperwork and maintain record in a more efficient and systematic way. This module will also help to calculate the number of leaves taken monthly annually and help gather data with respect to number of leaves, thereby helping in calculating the leaves working days by the HR Department. Snehal Vijay Kamble | Amruta Shivaji Kamble | Priyanka Sanjeev Babar | Sushmita Shrimant Kakmare | Mr. Nilesh D. Ghorpode "A Survey Paper on Leave Automation" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-2 , February 2019, URL: https://www.ijtsrd.com/papers/ijtsrd21370.pdf

Recently, the development of quantum chips has made great progress – the number of qubits is increasing and the fidelity is getting higher. However, qubits of these chips are not always fully connected, which sets additional barriers for implementing quantum algorithms and programming quantum programs. In this paper, we introduce a general circuit optimizing scheme, which can efficiently adjust and optimize quantum circuits according to arbitrary given qubits’ layout by adding additional quantum gates, exchanging qubits and merging single-qubit gates. Compared with the optimizing algorithm of IBM’s QISKit, the quantum gates consumed by our scheme is 74.7%, and the execution time is only 12.9% on average.

In this paper, we propose a dirty paper coding (DPC) scheme that uses trellis shaping for the overlay cognitive radio channel, where a cognitive user and a primary user transmit concurrently in the same spectrum. Interference of the primary user is assumed to be known at the cognitive transmitter non-causally. Based on this knowledge, the shaping code selection, as a key feature of the proposal, is introduced which enables the constellation to be self adaptively changed. The performance of our proposed scheme is compared using simulations with that based on the conventional trellis shaping and it achieves excellent tradeoff between performance and complexity.

We develop a system for generating embedded diagnostics from an ODE model that can isolate faults given the memory and processing limitations of the embedded processor. This system trades off diagnosis isolation accuracy for inference time and/or memory in a principled manner. We use a Polynomial Regression approach for tuning the performance of an ensemble of low-fidelity ODE diagnosis models such that we achieve the target of embedded processing limits. We demonstrate our approach on a non-linear tank benchmark system.

Rapid advancement in the domain of quantum technologies have opened up researchers to the real possibility of experimenting with quantum circuits, and simulating small-scale quantum programs. Nevertheless, the quality of currently available qubits and environmental noise pose a challenge in smooth execution of the quantum circuits. Therefore, efficient design automation flows for mapping a given algorithm to the Noisy Intermediate Scale Quantum (NISQ) computer becomes of utmost importance. State-of-the-art quantum design automation tools are primarily focused on reducing logical depth, gate count and qubit counts with recent emphasis on topology-aware (nearest-neighbour compliance) mapping. In this work, we extend the technology mapping flows to simultaneously consider the topology and gate fidelity constraints while keeping logical depth and gate count as optimization objectives. We provide a comprehensive problem formulation and multi-tier approach towards solving it. The proposed automation flow is compatible with commercial quantum computers, such as IBM QX and Rigetti. Our simulation results over 10 quantum circuit benchmarks, show that the fidelity of the circuit can be improved up to 3.37 × with an average improvement of 1.87 ×.

This paper describes the problem of intelligent paper grouping and its mathematical model. By optimizing and improving the traditional dynamic programming algorithm, its space complexity is reduced from O(nb) to O(b). At the same time, the flexibility of dynamic programming algorithm is increased by using marker function and tracking algorithm, and the result composition is tracked to obtain the optimal solution. Finally, through several experiments, the improved dynamic programming algorithm is compared with the greedy algorithm and brute force algorithm, and it is found that the improved dynamic programming algorithm has a very good result and is with high efficiency when applied to the simple test paper. It is the most recommended algorithm among the two algorithms compared in this paper.