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The program/erase process in floating gate (FG) flash memory devices is modeled by considering sequential quantum tunneling of electrons and taking into account quantum confinement in the channel and FG. We precisely determine location of quasi-bound or decaying quantum states in the inversion layer and in FG comprising a nanocrystal (NC) layer, and compute their lifetime by finding the complex eigenenergy of the resonance transmission problem. Self-consistent solutions to Poisson and Schrödinger equations are obtained for the quantum states of electrons in the inversion layer of MOS devices, and subsequently, sequential Fowler–Nordheim tunneling current to the spherical NCs is obtained using finite-element method considering open boundary conditions. The method described here is capable of determining the tunneling current accurately for arbitrary potential profiles, and can be applied for composite tunnel dielectric stacks. Our results show good agreement with the experimental data for high- $k$ interpoly dielectric flash memory devices. [ABSTRACT FROM PUBLISHER]

Heterogeneous SiN x based charge trap flash (CTF) which has varying N/Si ratio (x) along the thickness of the charge-trapping layer (CTL) shows improved program/erase (P/E) transients. In this work, we present the P/E model invoking different nature of traps in N-rich and Si-rich CTL and investigate the physical processes behind the P/E improvement observed in heterogeneous CTF. A set of coupled equations that include Poisson's and rate equations for electrons and holes are solved considering the variation of CTL physical parameters along the thickness. The electron/hole injection current is accurately computed by including quantum effects at Si/SiO 2 interface and taking into account the field-dependent relaxation of the energetic injected carriers. The simulation results of our model are in close agreement with the experimentally observed characteristics for five different sets of CTF devices with standard, Si-rich and N-rich homogeneous, and discretely and linearly graded heterogeneous CTF. Our study points out that the improvement in program transient for the heterogeneous CTF devices is attributed to the variation of trap density and trap energy along the CTL thickness and not due to lateral tunneling between the traps. The improvement in erase saturation and speed is due to high electron emission from the traps in Si-rich layer near bottom oxide of heterogeneous CTL. • The SiN x heterogeneous trap layer has a variation of N/Si ratio (x) along the thickness. • The Program/Erase model for flash having a heterogeneous trap layer is presented for the first time. • The model shows close agreement with the experimentally observed characteristics of 5 devices. • Improved program transient is shown due to the variation of trap energy and density. • Erase transient improvement is due to the presence of a Si-rich layer near bottom oxide. [ABSTRACT FROM AUTHOR]