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In this brief, a harmonic-controlled substrate-integrated defected ground structure (SIDGS) resonator with tuning capacitor is proposed for the design of tunable filter. Such resonator exhibits a harmonic-controlled characteristic. The fundamental resonant frequency can be properly tuned, while the spurious resonance is controlled at much higher frequency to achieve a wide stopband. To verify the principle, a tunable bandpass filter (BPF) is designed and fabricated based on the resonator. The center frequency can be tuned from 1.75 to 2.7 GHz. Meanwhile, the stopband can extend up to 9.5 GHz with a rejection level of 20 dB for all tuning cases. The BPF also exhibits low insertion loss (i.e., 1.1–1.9 dB) and compact size (i.e., 0.07 ${\lambda _{g}}\,\,{\times }\,\,0.08\,\,{\lambda _{g}}$ , where ${\lambda _{g}}$ is the microstrip guided wavelength at the 1.75 GHz). [ABSTRACT FROM AUTHOR]

In this article, a distributed-swing-boosting and harmonic-impedance-expanding multi-core oscillator is proposed to achieve low phase noise and high figure-of-merit (FoM), simultaneously. First, a distributed-coupling multi-core topology is introduced to reduce the chip area with no mode ambiguity. Then, the distributed-swing-boosting and harmonic-impedance-expanding structure is developed to boost the gate swing and square-like waveform of $V_{\text {DS}}$. The common-mode (CM) resonances around the second harmonic and the differential-mode (DM) resonances around the third harmonic are utilized to suppress the flicker noise up-conversion and achieve harmonic shaping. Meanwhile, the dual-resonance response expands the high-impedance frequency ranges around the harmonics, and thus, the effect of harmonic shaping can be obtained over a wide frequency range. Fabricated in a 40-nm CMOS process, the oscillator measured exhibits low phase noise and high FoM simultaneously with a compact chip size. The minimum phase noise is −138.9 dBc/Hz at the 1-MHz offset, corresponding to an FoM of 195.1 dBc/Hz. The 1/ $f^{3}$ phase noise corner is 100–130 kHz over the 26.6% tuning range. [ABSTRACT FROM AUTHOR]

A wideband hybrid mode-switching push–push oscillator with low phase noise is presented in this paper. To achieve the wide tuning range, the inductive and capacitive hybrid mode-switching technique is proposed for the first time. It introduces more freedom of design parameters (i.e., inductance and capacitance) in the resonant tank. Under certain tuning range requirement, the hybrid mode-switching oscillator achieves higher input impedance of the resonator compared to the conventional mode-switching oscillators. Meanwhile, a transformer-coupled inductor ring with symmetrical layout configuration is proposed to realize the switch-less hybrid mode switching, which further improves the circuit performance at sub-THz. Therefore, a good phase noise performance can be obtained within a wide tuning range, which leads to a relaxed tradeoff between the phase noise and tuning range. To verify the aforementioned mechanism operating at sub-THz band, a hybrid mode-switching oscillator based on the dual-mode push–push topology is proposed and fabricated in a conventional 28-nm CMOS technology. The measured results show a 21.7% tuning range with the center frequency of 169.6 GHz and a state-of-the-art FoMT of −180.6 dBc/Hz. The core circuit only occupies 0.039 mm2, while drawing 95 mW with a 0.9-V supply. [ABSTRACT FROM AUTHOR]

In this paper, two fully integrated digital power amplifiers (DPAs) intended for polar transmitters are proposed using a 40-nm CMOS technology, which achieve ultra wideband and high efficiency simultaneously. Firstly, the wideband Class-E power amplifier with nonideal characteristics is analyzed. Secondly, the design procedure of converting the nonideal Class-E model to a compact matching network is introduced for the on-chip implementation. Thirdly, the stacked-stepped-impedance transformer is utilized for the wideband output-matching network to improve the DPA power efficiency while tracking optimum load impedance. Finally, to enhance the saturated and back-off efficiency within a wideband, a novel feed-forward DPA architecture for a digital polar transmitter with multi-mode dynamic-matching (DM) network is firstly introduced and demonstrated. To verify the mechanism mentioned above, two DPAs are implemented and fabricated, which are the only reported wideband DPAs operating above 3 GHz with record fractional bandwidths, i.e., 92% and 100.8%, respectively. The proposed DPAs (i.e., DPA-I and DPA-II) exhibit peak output power of 22.2 and 22.3 dBm and peak drain efficiency of 46.2% and 47.4%, respectively, with a 1.2-V supply. In DM modes, the saturated and 6-dB back-off drain efficiency of DPA-II achieve maximum improvements of 7.5% and 5.7%, respectively. The core chip-sizes of the proposed DPAs (i.e., DPA-I and DPA-II) are 0.22 mm^2 and 0.24 mm^2, respectively. [ABSTRACT FROM PUBLISHER]