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Gallium nitride (GaN) devices are generally more prone to severe switching oscillations than Si mosfets due to their fast switching speeds. Different from Si and SiC mosfets, GaN devices typically have a lower maximum gate voltage rating. Taking the Efficient Power Conversion Corporation series as an example, the gate drive voltage is usually 5 V, but the maximum voltage rating is 6 V. Therefore, GaN devices are more susceptible to damage from gate-source voltage oscillation. In this letter, a gate drive circuit with a clamping function is proposed to suppress gate-source voltage oscillation. The adopted method can not only clamp the gate voltage of the GaN device near the drive voltage to protect the device, but also does not affect the switching speed of the device. The proposed method mainly uses some passive components that make the circuit design simpler compared with other active gate driver methods. Finally, the effectiveness of the proposed method is verified by experiments. [ABSTRACT FROM AUTHOR]

With high-temperature power devices available, the support circuitry required for efficient operation, such as a gate driver, is needed as part of a complete high-temperature solution. The design of an integrated silicon carbide (SiC) gate driver using a 1.2-μm complementary metal–oxide–semiconductor (CMOS) process is presented. Adjustable drive strength is added to facilitate a minimal external component requirement for high-temperature power modules and lays the groundwork for dynamic adjustment of drive strength. The adjustable drive strength feature demonstrates a capability of reducing overshoot and controlling dv/dt dynamically. Measurement of the gate driver was performed driving a power mosfet gate over temperature, exceeding 500 °C. High-speed and high-voltage room temperature evaluation is provided, demonstrating a system capable of high performance over temperature. The driver accomplishes better than 75 ns of rise and fall time driving the Cree CPM3-0900-0065B from room temperature to over 500 °C indicating that it will be ideal for integration into an all-SiC power module where driver, protection circuits, and power devices are fabricated in SiC. [ABSTRACT FROM AUTHOR]

This paper describes a silicon carbide pulse width modulation (PWM) signal generator in the 1.2 μm HiTSiC CMOS process developed by Raytheon Systems Ltd. The design features a 6-b binary input, which allows for setting a system's duty cycle. The results presented in this paper utilize a field programmable gate array board in the test setup to dynamically set the duty cycle by controlling each bit. A control current is also available to give the user added flexibility for tuning the duty cycle. Experimental results show the duty cycle range of the PWM generator to be between 4.7% and 95.2% at 400 °C. Sustained operation of the circuit is demonstrated over a period of 50 h at 300 °C. Finally, the PWM generator is evaluated in the operation of a boost converter. [ABSTRACT FROM PUBLISHER]

The need for dependable digital circuitry with the capability to operate reliably in high-temperature environments has been increasing drastically in applications such as automobile, aerospace, oil exploration, and power electronics. However, wide temperature swings significantly alter the threshold voltage of individual transistors, which adversely affects circuit timing in traditional synchronous designs. Such timing changes may in turn violates the setup and hold times of the clocked components, leading to potential circuit failure. This paper presents a complex digital integrated circuit design methodology using both synchronous and asynchronous logic for comparison in a young silicon carbide (SiC) design process developed by Raytheon UK. Seventeen circuits were designed, fabricated, and tested with results showing correct operation at temperatures at and above the target temperature of 300 °C. [ABSTRACT FROM PUBLISHER]

A compact model for SiC Power MOSFETs is presented. The model features a physical description of the channel current and internal capacitances and has been validated for dc, CV, and switching characteristics with measured data from a 1200-V, 20-A SiC power MOSFET in a temperature range of 25°C to 225°C. The peculiar variation of on-state resistance with temperature for SiC power MOSFETs has also been demonstrated through measurements and accounted for in the developed model. In order to improve the user experience with the model, a new datasheet driven parameter extraction strategy has been presented which requires only data available in device datasheets, to enable quick parameter extraction for off-the-shelf devices. Excellent agreement is shown between measurement and simulation using the presented model over the entire temperature range. [ABSTRACT FROM AUTHOR]

A practical parameter extraction procedure for a power silicon carbide (SiC) junction field-effect transistor (JFET) is presented. The carrier mobility and carrier concentration are very important parameters, strongly affecting the device current capability and dynamic characteristics for a given design. When modeling JFETs, the values of these parameters are usually based on assumptions and given by a vendor in a range. As a result, model accuracy is compromised. In this paper, a step-by-step parameter extraction procedure is described that includes the extraction of mobility and carrier concentration in the channel and drift regions based on knowledge of device geometrical parameters. For the first time, carrier mobilities in the channel and drift regions of a power JFET are extracted individually. It is found that channel and drift region mobilities can be very different for a given device since they are strongly dependent on the fabrication process. The separate extraction of these two mobilities can also improve model accuracy in the case of imperfect knowledge of the device geometry. The developed procedure includes the extraction of empirical parameters describing the temperature dependence of mobilities in the channel and drift regions. A simple static I– V characterization and C–V measurements are the only measurements required for the parameter extraction. In this paper, the procedure is experimentally validated for both normally off (enhancement mode) and normally on (depletion mode) JFETs. [ABSTRACT FROM AUTHOR]

A novel SiC junction field-effect transistor (JFET) model that uses a unified description of linear and saturated conduction modes is proposed. Advantages of the proposed model are improved robustness and convergence, inclusion of field-dependent mobility effects, and more physical description of the current saturation phenomenon. The model is validated against a normally off JFET sample over a wide temperature range. Finite-element simulations are used to demonstrate the physics-based nature of the proposed model. [ABSTRACT FROM AUTHOR]

In this paper, a physical model for a SiC Junction Field Effect Transistor (JFET) is presented. The novel feature of the model is that the mobility dependence on both temperature and electric field is taken into account. This is particularly important for high-current power devices where the maximum conduction current is limited by drift velocity saturation in the channel. The model equations are described in detail, emphasizing the differences introduced by the field-dependent mobility model. The model is then implemented in Pspice. Both static and dynamic simulation results are given. The results are validated with experimental results under static conditions and under resistive and inductive switching conditions. [ABSTRACT FROM AUTHOR]