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We develop a tri-state memristive system based on composable binarized memristors, from both a dynamical systems construction to the development of in-house fabricated devices. Firstly, based on the SPICE model of the binary memristor, the series and parallel circuits of binary memristors are designed, and the characteristics of each circuit are analyzed in detail. Secondly, through the analysis of the connection direction and parameters of the two binary memristors, an effective method to construct a tri-state memristor is proposed, and verified using SPICE simulations. Finally, the characteristics of the constructed equivalent tri-state memristor are analyzed, and it is concluded that the amplitude, frequency and type of the input signal can affect the characteristics of the equivalent tri-state memristor. Predictions from this modeling were validated experimentally using Au/ Nb 2 O 5 /Nb cross-point devices. [ABSTRACT FROM AUTHOR]

The human retina sends visual signals to the brain's visual cortex from photoreceptors (rod and cone cells) through various synaptic pathways and performs crucial early vision processing before signals are passed to higher brain regions. Herein, an artificial retina system implemented based on the leaky integrate‐and‐fire spiking neuron model is presented. The architecture of the proposed retina system consists of a multilayer convolutional neural network (CNN), and the system uses spike timing‐dependent plasticity (STDP) as a feedforward learning rule. In addition, the system integrates a feedback plasticity learning rule to expedite learning convergence. The system weights are implemented using nanoscale memristor arrays, taking on a constrained (radix‐X) range of conductance states. The proposed system produces an output image of 25 × 25 pixels, corresponding to the output retina ganglion cells that act as the interface between the retina and the visual cortex, using an input image of 100 × 100 pixels. [ABSTRACT FROM AUTHOR]

Memristors are passive non‐linear circuit components with memory characteristics, and have been recognized as the fourth basic circuit component, along with resistors, capacitors, and inductors. It has been nearly half a century since the conceptualisation of the memristor, and related research has mainly focussed on the two aspects of binary and continuous memristors. However, compared with these two types of memristors, tri‐state and multi‐state memristors have greater data density per device, with rich dynamics and great potential in logic and chaotic circuit applications. Moreover, previous studies show that the series‐parallel connection of memristor generates more diverse circuit behaviours and increased capacity over a single memristor. However, most of this research is based on mathematical analysis, and lack behavioural circuit simulations or experimental validation. Here, the tri‐state memristor is proposed and the mathematic and equivalent Spice models of the tri‐state memristor is shown. Furthermore, the circuit characteristics are studied with a complete characterisation of its series‐parallel behaviours of the tri‐state memristor. Simulations are performed with LTSpice, and the results verify the theoretical analysis, which provides a strong experimental basis for the study of combinational memristive circuits. [ABSTRACT FROM AUTHOR]

Stochastic Computing (SC) is a computing paradigm that allows for the low-cost and low-power computation of various arithmetic operations using stochastic bit streams and digital logic. In contrast to conventional representation schemes used within the binary domain, the sequence of bit streams in the stochastic domain is inconsequential, and computation is usually non-deterministic. In this brief, we exploit the stochasticity during switching of probabilistic Conductive Bridging RAM (CBRAM) devices to efficiently generate stochastic bit streams in order to perform Deep Learning (DL) parameter optimization, reducing the size of Multiply and Accumulate (MAC) units by 5 orders of magnitude. We demonstrate that in using a 40-nm Complementary Metal Oxide Semiconductor (CMOS) process our scalable architecture occupies 1.55mm2 and consumes approximately 167 μW when optimizing parameters of a Convolutional Neural Network (CNN) while it is being trained for a character recognition task, observing no notable reduction in accuracy post-training. [ABSTRACT FROM AUTHOR]

The ever‐increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes inspiration from the highly parallel, low‐power, high‐speed, and noise‐tolerant computing capabilities of the brain, may provide such a shift. Many researchers from across academia and industry have been studying materials, devices, circuits, and systems, to implement some of the functions of networks of neurons and synapses to develop neuromorphic computing platforms. These platforms are being designed using various hardware technologies, including the well‐established complementary metal‐oxide semiconductor (CMOS), and emerging memristive technologies such as SiOx‐based memristors. Herein, recent progress in CMOS, SiOx‐based memristive, and mixed CMOS‐memristive hardware for neuromorphic systems is highlighted. New and published results from various devices are provided that are developed to replicate selected functions of neurons, synapses, and simple spiking networks. It is shown that the CMOS and memristive devices are assembled in different neuromorphic learning platforms to perform simple cognitive tasks such as classification of spike rate‐based patterns or handwritten digits. Herein, it is envisioned that what is demonstrated is useful to the unconventional computing research community by providing insights into advances in neuromorphic hardware technologies. [ABSTRACT FROM AUTHOR]

In large-scale high-density integrated circuits, memristors in close proximity to one another both influence, and are influenced by, the behavior of nearby memristors. However, the previous analyses of memristors-based circuit applications have seldom considered the possibility of coupling effects between memristors which invariably influences the response of all memristors, thus rendering much previous research as incomplete. In this paper, the circuit dynamics of memristive Chua's circuits are systematically analyzed based on a pair of compositely connected flux-controlled memristors characterized by cubic nonlinearity as a typical example. A theoretical analysis is undertaken and verified via MATLAB. While tuning the coupling strength, variations in circuit dynamics are characterized by phase portraits, bifurcation diagrams, and Lyapunov exponents. A new floating memristor emulator with coupling ports, described by cubic nonlinearity, is designed using off-the-shelf circuit devices and is shown to be successfully used in building chaotic circuits in hardware experiments, verifying theoretical results in simulations. This paper provides a new way through which memristors-based circuit dynamics can be influenced by tuning the coupling strength between memristors without changing other circuit parameters. It is further highlighted that when designing future memristors-based circuits, the coupling action between memristors should be considered if necessary and compensated when causing undesired circuit responses. [ABSTRACT FROM AUTHOR]

The packing density associated with crossbar arrays offers important architectural solutions to numerous forms of computational engines. Mitigation of sneak paths in the crossbar array, however, requires additional layers in fabrication technology to impede current flow in order to avoid undesired changes to the state when reading and writing to and from the array. This results in an unavoidable increase in the vertical stacking dimension of the array. With the recent emergence of bistable memristors under both dc and ac, by adopting their asymptotic dynamics, we realize a significant improvement in memory construct and spatial constraints of memristor crossbar arrays. In this brief, we formalize a method of configuring a whole array architecture to any permutation of states without sacrificing array density by using a rigorous theoretical analysis, and confirmed via simulation. [ABSTRACT FROM AUTHOR]