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Ultra-thin epitaxially grown Si layers have been used for Ge surface passivation in CMOS devices utilizing standard silicon SiO2/HfO2 gate stack. In this work, we propose a high-k TmSiO interfacial layer, which has shown excellent performance on Si, instead of the chemical SiO2. We successfully transfer a TmSiO/Tm2O3/HfO2 gate stack from silicon to Si-passivated Ge devices, yielding interface state density of 3·1011 eV-1cm-2, which is comparable to GeOx passivation. Moreover, Si-capped Ge gates with TmSiO interfacial layer achieve significant improvement in oxide trap density compared to GeOx passivation, exhibiting a potential for superior reliability. We further investigate the robustness of Si layer growth process and show that small (±3 °C) variations of growth temperature can be detrimental to the interface state density of the gate stacks., QC 20201202

A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices., QC 20211004

A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices., QC 20180611

The authors have studied the reaction between a Ge (100) substrate and thin layers of Ni ranging from 2 to 10 nm in thickness. The formation of metal-rich Ni5Ge3 was found to precede that of the monogermanide NiGe by means of real-time in situ x-ray diffraction during ramp-annealing and ex situ x-ray pole figure analyses for phase identification. The observed sequential growth of Ni5Ge3 and NiGe with such thin Ni layers is different from the previously reported simultaneous growth with thicker Ni layers. The phase transformation from Ni5Ge3 to NiGe was found to be nucleationcontrolled for Ni thicknesses < 5 nm, which is well supported by thermodynamic considerations. Specifically, the temperature for the NiGe formation increased with decreasing Ni (rather Ni5Ge3) thickness below 5 nm. In combination with sheet resistance measurement and microscopic surface inspection of samples annealed with a standard rapid thermal processing, the temperature range for achieving morphologically stable NiGe layers was identified for this standard annealing process. As expected, it was found to be strongly dependent on the initial Ni thickness.

Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable., QC 20170224

This study presents signal-to-noise ratio (SNR) measurements of single crystalline dots or layers of SiGe/Si in multilayer structures in terms of Ge content, interfacial and layer quality. All multilayers were processed in form of mesas and the noise behavior of electrical signal was investigated by comparing the power spectral density curves and K1/f values. The SiGe/Si multilayer structures were also characterized by the conventional material analysis tools and the results were compared to the noise measurements. The quality of SiGe/Si interface or SiGe layer was monitored by intentional exposure to oxygen in range of 2–1600 nTorr either during or prior to SiGe growth. The results demonstrated that SNR was sensitive to the interfacial and layer quality, and the Ge content in a multilayer structure. The noise level became very high when the strain fluctuated within SiGe layer and this occurred for SiGe with high Ge content or SiGe dots., QC 20160823

This work investigates the crystal quality of SiGe layers grown at low temperatures using trisilane, and germane precursors. The crystal quality sensitivity was monitored for hydrogen chloride and/or minor oxygen amount during SiGe epitaxy or at the interface of SiGe/Si layers. The quality of the epi-layerswas examined by quantifying noise parameter, K-1/f obtained from the power spectral density vs. 1/f curves. The results indicate that while it is difficult to detect small defect densities in SiGe layers by physical material characterization, the noise measurement could reveal the effects of oxygen contamination as low as 0.16mPa inside and in the interface of the layers., QC 20160913

QS 2015

Pattern dependency of selective epitaxy of Si1-xGex (0.20 ≤ x ≤ 0.45) grown in recessed source/drain regions of 22 nm pMOSFETs has been studied. A complete substrate mapping over 200 mm wafers was performed and the transistors' characteristics were measured. The designed SiGe profile included a layer with Ge content of 40% at the bottom of recess (40 nm) and capped with 20% Ge as a sacrificial layer (20 nm) for silicide formation. The induced strain in the channel was simulated before and after silicidation. The variation of strain was localized and its effect on the transistors' performance was determined. The chips had a variety of SiGe profile depending on their distance (closest, intermediate and central) from the edge of the 200 mm wafer. SiGe layers with poor epi-quality were observed when the coverage of exposed Si of the chip was below 1%. This causes high Ge contents with layer thicknesses above the critical thickness., QC 20151127

In this study, Ge1-x-y-zSnxSiyCz layers (0.01≤x≤ 0.06, 0≤y≤0.02 and 0≤z≤0.01) have been successfully grown at 280-330 °C on Ge and Si by using RPCVD technique. It was demonstrated that the quality of epitaxial layers is dependent on the growth parameters, layer thickness and the quality of Ge virtual layer. It was found that a proper strain balance in the matrix during the epitaxy where the Si is adjusted carefully with the Sn flux improves the incorporation of Sn in Ge matrix. A similar improvement of Sn incorporation has been observed for phosphorous, boron and carbon doping in GeSn layers as well. This is explained by the compensation of the compressive strain caused by Snand the tensile strain induced by Si to obtain the minimum energy in Ge matrix. This behavior was not observed for relaxed GeSn layers and Sn incorporation could be controlled only by the growth parameters. The thermal stability of GeSn is an important integration issue for device fabrication. The thermal stability of P- and B-doped GeSn layers was studied by rapid thermal annealing (RTA) in range of 400-600 °C and compared with intrinsic layers. The GeSn layers were stable up to 550 °C while the B-doped layers showed strain relaxation readily at 500 °C. The epitaxial quality of epi-layers was evaluated in terms of oxygen and water vapor contamination. The level of oxygen during epitaxy was as low as 10 ppb and the contamination amount was found as low as 1017 cm-3., QC 20150609

A novel interfacial energy driven colloidal lithography technique to fabricate periodic patterns from solution-phase is presented and the feasibility and versatility of the technique is demonstrated by fabricating periodically arranged ZnO nanowire ensembles on Si substrates. The pattern fabrication method exploits different interfaces formed by sol-gel derived ZnO seed solution on a hydrophobic Si surface covered by a monolayer of colloidal silica spheres. While the hydrophobic Si surface prevents wetting by the seed solution, the wedge shaped regions surrounding the contact point between the colloidal particles and the Si substrate trap the solution due to interfacial forces. This technique allows fabrication of uniform 2D micropatterns of ZnO seed particles on the Si substrate. A hydrothermal technique is then used to grow well-defined periodic assemblies of ZnO nanowires. Tunability is demonstrated in the dimensions of the patterns by using silica spheres with different diameters. The experimental data show that the periodic ZnO nanowire assembly suppresses the total reflectivity of bare Si by more than a factor of 2 in the wavelength range 400-1300 nm. Finite-difference time-domain simulations of the wavelength-dependent reflectivity show good qualitative agreement with the experiments. The demonstrated method is also applicable for other materials synthesized by solution chemistry., QC 20140912

In this study, the formation of Ni-(GeSn)x on strained and relaxed Ge1-xSnx (0.01≤x≤ 0.03) nanowires in contact areas has been investigated. The epi-layers were grown at different temperatures (290 to 380°C) by RPCVD technique. The strain in GeSn layers tailored through carefully chosen of growth parameters and virtual substrate. The nanowires were fabricated through both I-line and dry-etching. 15 nm Ni was deposited either on the contact areas or whole length of nanowires. The wires went through rapid thermal annealing at intervals of 360 to 550°C for 30s in N2 ambient. The results show the thermal stability and amount of particular phases were strain-dependent. The formation of Ni-GeSn was eased when GeSn layers were strain-free. When the Sn content is high the epi-layers suffer from Sn segregation. The Sn-rich surface impedes remarkably the Ni diffusion. The electrical conductivity measurement of nanowires shows low resistivity and Ohmic contact are obtained for Ni-GeSn., QC 20150610

SiGe has been widely used for source/drain (S/D) engineering in pMOSFETs to enhance channel mobility. In this study, selective Si1-xGex growth (0.25 <= x <= 0.35) with boron concentration of 1-3 x 10(20) cm(-3) in the process for 22 nm node complementary metal-oxide semiconductor (CMOS) has been investigated and optimized. The growth parameters were carefully tuned to achieve deposition of high quality and highly strained material. The thermal budget was decreased to 800 degrees C to suppress dopant diffusion, to minimize Si loss in S/D recesses, and to preserve the S/D recess shape. Two layers of Si1-xGex were deposited: a bottom layer with high Ge content (x = 0.35) which filled the recess and a cap layer with low Ge content (x = 0.25) which was elevated in the S/D regions. The elevated SiGe cap layer was intended to be consumed during the Ni-silicidation process in order to avoid strain reduction in the channel region arising from strain relaxation in SiGe S/D. In this study, a kinetic gas model was also applied to predict the pattern dependency of the growth and to determine the epi-profile in different transistor arrays. The input parameters include growth temperature, partial pressures of reactant gases, and chip layout. By using this model, the number of test wafers for epitaxy experiments can be decreased significantly. When the epitaxy process parameters can be readily predicted by the model for epi-profile control in an advanced chip design, fast and cost-effective process development can be achieved., QC 20131111

We present fabrication and optical characterization of Si microstructure-ZnO nanowire (NWs) hierarchical structures for light management. Random and periodic hierarchical structures constituting Si micro pillar or micro pyramid arrays with overgrown ZnO NWs have been fabricated. Inexpensive colloidal lithography in combination with dry and wet chemical etching is used to fabricate Si microstructures, and ZnO NWs are grown by hydrothermal synthesis. The periodic Si micro pyramid-ZnO NWs hierarchical structure shows broadband antireflection with average reflectance as low as 2.5% in the 300-1000 nm wavelength range. A tenfold enhancement in Raman intensity is observed in this structure compared to planar Si sample. These hierarchical structures with enriched optical properties and high surface to volume ratio are promising for photovoltaic (PV) and sensor applications., QC 20130902