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The increasing use of Cu/low-k dielectrics as multilevel interconnect inclusion materials and aggressive scaling in advanced back-end of line (BEOL) results in a considerable challenge in the structural enhancement of mechanical reliability. Owing to the expected adoption of various ultra dielectrics, the development of a prediction methodology with reliable virtual prototypes is needed before realizing successful integrated circuits (IC) for the next technology node. These prototypes are required to assess the potentiality of interfacial cracks in dissimilar materials, while the impacts of chemical-mechanical polishing (CMP) and packaging are introduced. In order to meet the diversity of a Cu/low-k material system and to resolve the significant size difference between the interconnects and the whole IC device, this research presents finite element (FE) analysis based on the mechanic theory of interfacial fracture integrated with a global/local sub-modeling approach. The unique feature of the proposed novel concept is the adoption of equivalent stacked low-k interconnects within the analysis of a global FE model. Through estimation of the J-integral approach and verification of the four-point bending test (4-PBT), the methodology presented exhibits excellent numerical precision in predicting the cracking energy of low-k packaging. In addition, interfacial fracture parameters and stress fields acting near the crack tip are evaluated using an analytical solution combined with polynomial regressions. The derived results match well compared with the simulated data. Based on the presented demonstrations on the ability of simulated procedures, this investigation provides a desirable manner of understanding the related failure mechanisms of low-k interconnects.

Interfacial crack/delamination, due to the presence of dissimilar material systems, is one of the major concerns of thermo-mechanical reliability for the development of next node technology in integrated circuits (IC) devices. The cracking energy results from many back end of line (BEOL) and packaging processes at various temperature differences is prone to drive the crack advance. To investigate the sensitivity of crack propagation in low-k dielectric materials, a robust estimation of J-integral approach combined with a rectangular path of integral contour is performed using finite element analysis (FEA). By means of the verification of 4-point bending test (4-PBT), excellent agreements are obtained as compared with the experimental data. Moreover, a multiscale modeling technique is proposed to resolve the difficulty of model construction as from bridge device level to packaging level. The sub-modeling procedures developed specifically for the impact prediction of interfacial crack in complicated Cu/low-k interconnects. The analytic results indicate the foregoing methodology is valuable to forecast the physical behavior and reliability of advanced IC devices in the nano scaled size. On the basis of the presented results in this research, an approximated criterion for determining the dimensions of sub-model is suggested and demonstrated as well.

As the progress of the semiconductor process develops to achieve miniaturization and attain better performances for the electronic device, next-generation IC chips with deep sub-micron Cu/low-k stacked structures adopting the fabrication of (dual) damascene are developed to meet the urgent requirements of reducing high RC delay; the purpose of this is to obtain high-speed signal communication. However, due to poor adhesion and intrinsically lower fracture toughness of low-k materials as well as process loading that introduces flaws and delaminations, the phenomenon of crack growth is observed. To investigate the large scale difference problem, such as the back end of line (BEoL) structure to the silicon chip, a special multi-scale finite element simulation technology, global-local finite element method, is used to deal with this issue. The interfacial crack in the BEoL structure is modeled using the global-local technique. The chemical vapor deposition (CVD) process that induced loading to a micro crack in the interface between etch stop layer and metal track layer (ESL/Mx interface) will also be discussed through a statistical factorial design method in order to understand the crack growth phenomena that might occur during the BEoL process.

In order to resolve the issues of RC time delay and high power consumption, IC chips with Cu/low-k interconnects are developed to meet the foregoing requirements. However, there is a high potential that in doing so it may contribute to interfacial cracks occurring or propagating between the copper metal and the low-k dielectric material as a result of poor adhesion and lower fracture toughness, which results from the inherent mechanical imperfection of low-k materials. This fracturing problem is one of the most urgent issues for the thermomechanical reliability of Cu/low-k interconnects, and it needs to be resolved urgently. For this reason, we propose a prediction methodology of finite-element analysis (FEA) based on J-integral value estimation to investigate the interfacial fracture opportunity of low-k packages. However, the J-integral calculation is path dependent and so crucial in FEA for a crack on an interface between dissimilar materials. Therefore, various paths with an integral contour surrounding the crack tip are considered to avoid a misunderstanding of the cracking energy. All the analytic results indicate that a rectangular contour with a proper ratio of length/width, and multilayers of element close to the delaminating surfaces, is suggested for obtaining a stable J-integral value. On the other hand, the proposed methodology has been validated by a four-point bending test and compared with the relative experimental data of multi-low-k dielectric films. Moreover, under a reliable integral contour path that crack driving force predicted using the type of interfacial crack constructed by means of the element death technique, it shows good agreement with the simulated results of embedding actual crack.

As the electronics industry continues its efforts in miniaturizing the integrated circuit (IC), an IC chip with copper/low- k stacked back end of line (BEoL) structures has been developed for reducing RC delay in order to obtain high-speed signal communication. However, its reliability might become a concern due to the considerably lower adhesive strength as well as greater coefficient of thermal expansion (CTE) of the low- k materials. In this paper, the four-point bending technique is used to quantify the adhesion energy ( G C ). The global local finite element method, including the specified boundary condition (SBC) method and the multi-point constrain (MPC) method, is validated by the four-point bending experiment and is employed as a bridge to estimate the impact from package level to the deep sub-micron BEoL structure of the plastic ball grid array (PBGA) package. A crack driving force of 1.8 J/m 2 acting on the BEoL structure is obtained when the curing process of the moulding compound is performed.

As the technology of the semiconductor process continues to move forward, the next generation IC chip with copper/low-k stacked structures is being developed for reducing the RC delay in order to obtain high-speed signal communication. However, there is a high potential that in doing so it may contribute to interfacial cracks occurring or propagating between the copper interconnections and the low-k material as a result of poor adhesion and lower fracture toughness of the low-k material when temperature loads are applied during the wafer level and the packaging level stages. This fracturing problem is one of the most urgent issues for the thermo-mechanical reliability of a copper/low-k damascene module, and it needs to be resolved urgently. With the simulation of an interfacial fracture based on J-integral value estimation, the interfacial crack growth can be modeled using a finite element analysis (FEA) and compared it to Jc, which is interfacial fracture toughness that must be determined experimentally. Therefore, the stability of the J-integral value obtained from the FEA is crucial so as to avoid a misunderstanding of the cracking energy. In order to discuss the mesh density affecting the convergence of the J-value, various paths with an integral contour surrounding the crack tip are considered in this research. The interfacial crack is constructed using the element birth and death technique to suppose that an actual crack developed between copper/low-k interfaces. The analytic results show that the J-value will converge toward unity when a rectangular contour with a proper ratio of length/width, and multi-layers of element close to the delaminating surfaces are applied to reduce the loss of numerical analysis in precise. It should be noted that the crack tip must be at the center of the integral contour. The long side of the rectangular contour needs to be parallel to the direction of the fracture propagation. On the other hand, the curve of the J-value versus the increase of the crack length calculated from the model with the actual crack embedded shows good agreement with the simulated results with the virtual crack by means of the element birth and death technique

The die edge-seals and circuit under fad (CUF) are structurally optimized through 3D finite element analysis (FEA). Die edge-seals having the mechanically reinforced structure units are demonstrated essential. It is also shown that FEA help extract useful structural design concepts for CUP. The Poisson effects leading to a dual-ring-shaped high stress distribution area are confirmed to be detrimental for wire bonding and wire-pull tests. Excellent agreements are obtained as compared with the experimental data

The process development, characterization and performance evaluation of low-k dielectrics to form multi-level Cu interconnects for the 65 nm CMOS technology node are presented. Significant modifications and improvements over 90nm node have been implemented to overcome those challenges as design rules shrink, which include top via corner rounding control for the robust EM/SM reliability, and inline e-beam inspection for via/trench processes optimization. An in-house developed ECP additive "Trameca" for good Cu gap filling and a controllable hump height for good CMP performance are adopted to achieve tight Rs distributions. The facts that 100% yields of 2.1 millions via chain structure and open/short free on 5m long comb/meander structures along with SM/EM meeting the spec all demonstrated the technology to be a highly manufacturable BEOL process for 65 nm technology node.

A completely new concept for designing the illumination aperture filter is suggested. From experimental or simulative methods, we have extracted the performance of every individual beam component on the illumination plane. The optimal apertures are then obtained by superimposing the best components that meet the requirements demanded by the specific photo process. Different kinds of optimal apertures were successfully implanted to deal with different process problems. Therefore, it is called the customized illumination aperture filter (CIF). The zero 1D OPE CIF, as a proof of concept, was designed to eliminate the OPE of low k1 process. Without any OPC, 0.6micrometers DOF of the common ED window was obtained, where k1 equals 0.39 for our NA equals 0.55 stepper to print. 0.18 micrometers line patterns, T push to smaller k1, another CIF was designed to maximize the individual DOF and overcome the reduced power problem accompanied with the typical aggressive OAI. Using this CIF, we achieved 1.1 micrometers common DOF with 7 percent EL for 0.18 micrometers lien patterns. The CIF doubles the power of the Nikon's strong quadrupole, shrine. An ultimate resolution limit of 0.11 micrometers line pattern was reached as well with the CIF. Finally, a contact/via CIF was designed combined with a halt-tone PSM. The CIF gives about 0.8 micrometers common DOF with 7 percent EL for 0.2 micrometers holes and 0.7 micrometers DOF for 0.17 holes using thinner resist. The CIF approach is, therefore, proven to be a cost effective and relatively easy realizable alternative to the alternating PSM for extremely low k1 process applications.

Finding high performance and low cost anti-reflection strategies is a common goal for all photolithographers. This task is getting tough for dual damascene process than the metal-etch process because the oxide thickness variation enhances the thin film interference effect. In this paper, different ARC strategies using organic and inorganic material were examined to compare their CD control performance in sub-0.81micrometers dual damascene structure for KrF 248nm lithography. The organic bottom ARC (BARC) achieves reflectivity control through modulation its thickness. The first and second minimal points in BARC swing curve were chosen as the film thickness to be evaluated. The inorganic ARC, which referred to dielectric ARC (DARC) using PECVD silicon oxynitride in this article, was investigated with single layer and double layers structures. The double- layer DARC structure consists of two layers with different extinction coefficient K values. The optimal refractive index and thickness of each ARC structure were calculated from some available photolithography simulators. A PECVD process for DARC growth that provides easily tunable range of refractive index and thickness was established to meet the DUV process requirement from simulation. The performances of each ARC structure were evaluated on patterning 0.18 micrometers trench and 0.20 micrometers via in back-end- of-line dual damascene process. It showed that the double- layer DARC provided the most effective CD control ability among these ARC structures. The double-layer DARC should be one of the most potential candidates for sub-0.18 micrometers dual damascene process.