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This paper presents a multi-user Lab-as-a-Service solution based on representational state transfer (REST) architecture for manual and automated online measurements. The hardware part of the system consists of devices under test (DUTs), measurement equipment that is connected to a measurement computer, server computer with GlassFish application server and PostgreSQL database. Designed application programming interface (API) is briefly described. Using this API, users can write programs in LabVIEW that send measurement requests to the server and receive measured data. The system has been tested in multi-user mode with 10 simultaneous online users.

This paper describes implementation of four lumped element quadrature couplers in a standard 0.18 um CMOS technology for 4.8-5.0 GHz band. Simulation results after layout parasitic extraction and comparison with the worst corner case are presented.

This paper presents simulation results of an inductorless vector modulator in a standard 65 nm CMOS technology. The designed modulator is based on a vector-sum phase shifter and for five bit amplitude resolution and six bit phase resolution demonstrates 0.2 dB and 1.0 deg. RMS amplitude and RMS phase error in 4-6 GHz band. Input CP1dB is about –7.8 dBm with power consumption of 31 mW and maximum gain of 1.9 dB at 4.9 GHz.

Attenuators and phase shifters which are the circuits for amplitude-phase distribution control are key elements of antenna arrays. Dispersion of technology parameters results in deviation of the characteristics of integral circuits from rated values that requires application of the techniques for this effect compensation. In this paper there are considered the methods for development and calibration of the circuits in a basis of vector-sum signals allowing to modify both amplitude and phase of input high-frequency signal. It is proposed the method of calibration on a basis of interpolation of measured dependences of absolute value and phase of transfer factor on controlling voltage. Application of proposed method for calibration of vector phase shifter with operating frequency band 2.8–3.2 GHz fabricated with 0.18 mm CMOS allows to provide mean square deviation of phase error is not greater than 0.9°. At that amount of required measurements is 20 times decreased comparing known approach on a basis of measurement of all amplitude-phase states.

Electronic scanning is widely used in radar systems. Fifth generation (5G) communication systems are highly relying on the same principle. Different beamforming techniques, such as digital, analog and hybrid, are studied and compared in theory by many authors during the search of optimal architecture in sense of energy and spectral efficiency. Several integrated solutions have been designed and published by university researches and commercial companies. In this paper some of the recent publications about beamforming techniques and integrated circuits for sub-6 GHz and sub-30 GHz are discussed and compared.

RFID-tags are conventionally provided for various things. A RFID system for Internet of Nano Things based on a UMC 180nm CMOS integrated circuit was proposed. The system is intended for identification of tags realized on a surface-acoustic-wave delay lines and designed as a transceiver front-end with operating frequency range of 2.40–2.48 GHz. A polling signal is a stepped frequency chirp, and the read range makes up 3 m.

This paper presents a novel unbalanced transformerless vector-sum phase shifter architecture. The proposed approach is based on the forming of four signals from the input unbalanced signal by an RC quadrature all-pass filter. These signals are subtracted to obtain a pair of orthogonal signals which are added on the load network of the Gilbert cells with weighted coefficients to form the differential phase shifted signal. The common-mode component of the phase shifted signal is suppressed by the following circuits. The resulting signal is transformed to the single-ended form and amplified. According the proposed architecture 6-bit vector-sum phase shifter has been designed and simulated in 0.18 um CMOS process. The RF part of the circuit consists of an RC quadrature all-pass filter, variable gain amplifiers, a common-mode rejection circuit, an active combiner and a power amplifier. The phase shifter operates in the 3.4–4.2 GHz range. Simulation results show a maximum gain of 3.7 dB with 0.4 dB variation, a maximum phase error and a root-mean-square phase error less than 1.5 degree and 0.7 degree respectively. The current consumption of the RF part is 39.5 mA from a 1.8 V supply voltage.

This paper reviews efficient amplification techniques, such as a load modulation, an envelope tracking (ET), an envelope elimination and restoration (EER), an outphasing and a digital modulation for signals with high peak-to-average power ratio (PAPR). Implementations of these techniques in the state-of-art CMOS power amplifiers are compared.

Cascode class-E power amplifier in 180/350 nm CMOS for envelope elimination and restoration system is presented. Designed amplifier achieves 21 dBm output power and 44% PAE at 1900 MHz with 3 V supply voltage. Charging acceleration technique is used for efficiency enhancement. ESD protection problem is discussed.