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A high-resolution, dynamically programmable analog-to-digital converter (ADC) which uses the phase modulation-demodulation low-pass architecture and on-chip digital filtering for radar and communications applications is presented.

A digital channelizer circuit, containing more than 10,000 Josephson junctions integrated with lowpass and bandpass ADCs which demonstrate a set of single-chip digital RF receivers is presented.

A compact superconducting millimeter/submillimeter integrated digital spectrometer is developed. This spectrometer can be used in radio-astronomical research, remote monitoring of the Earth atmosphere and environmental monitoring for hazardous materials of chemical and biological origin.

Clock sources for rapid single flux quantum (RSFQ) digital circuits using high-quality long Josephson junction (LJJ) resonant oscillators of annular geometry is developed. The annular LJJ oscillator demonstrated a high quality factor, as it represented a topologically closed system, unperturbed by reflection from boundaries and collisions among the fluxons.

The design, fabrication and testing of a two-stage direct current superconducting quantum interference device (SQUID) is presented. The device, derived from a low frequency amplifier, has an effective input inductance of about 2.9 microH, a SQUID's inductance of about 11pH and an effective coupling k2 of about 0.24. A modified distributed damping filter and coupling transformer geometry suppress the influences of resonances and external noise in the SQUID microstructure.

HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency. The complete system, consisting of a cryopackaged Nb superconductor All-Digital Receiver (ADR) chip followed by room-temperature interface electronics and a field-programmable gate array (FPGA) based post-processing module, has been developed. Depending on the targeted application the ADR chip comprised either a low-pass delta with phase modulation-demodulation architecture or X-band band-pass sigma-delta modulators together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chips were fabricated using a 4.5-kA/cm2 HYPRES process and were cryopackaged using a commercial-off-the-shelf cryocooler. Recently, with significant improvements in chip cryopackage, room-temperature electronics and FPGA programming we were able to achieve stable operation of a low-pass ADR at 28.16 GHz and X-band ADR at 30.72 GHz clock frequencies. Experimental results are presented and discussed. [ABSTRACT FROM AUTHOR]

We describe several improvements that are being pursued to improve the dynamic range of lowpass phase modulation- demodulation (PMD) analog-to-digital converters (ADC). The existing ADC has been tested at sampling frequencies up to 29.44 GHz; a 89.15 dB signal to noise ratio (SNR) is achieved for a 10 MHz sinusoidal input, with the noise being measured in a reference 10 MHz bandwidth in the decimated band. The first improved approach involves a multi-rate ADC where the modulator sampling frequency is increased in multiples of the decimation filter clock. We have tested the multi-rate ADCs at sampling frequencies up to 46.08 GHz and 29.44 GHz for chips fabricated using the 4.5 and 1 kA/cm2 fabrication processes respectively. For a single channel ADC, with a 9.92 MHz sinusoidal input, sampled at 29.44 GHz, the SNR is 83.93 dB in a reference 10 MHz bandwidth. The spur-free dynamic range (SFDR) is 95 dB. In another improved architecture, called the quarter-rate ADC, the modified quantizer quadruples the input dynamic range by distributing the input in a cyclical fashion to four output channels, each operating at a quarter of the fiuxon transport rate. This enables quadrupling the synchronizer channels, providing an opportunity for up to 12 dB performance enhancement. A parallel counter following the multi-channel synchronizer converts the differential code to a multi-bit binary code, which is further processed by the decimation filter. A prototype version of this ADC with a two channel synchronizer, fabricated using the 4.5 kA/cm2 process, has been tested up to a sampling frequency of 25.6 GHz. For a 10 MHz sinusoidal input, the SNR is 82.54 dB, with the noise measured in a reference 10 MHz band- width. We are also designing a subranging ADC with two PMD front-ends. Simulation results promise greater than 20 dB performance enhancement. [ABSTRACT FROM AUTHOR]