Search

This brief presents a compact gated ring oscillator (GRO) based cyclic time-to-digital converter (TDC) for single-photon emission computed tomography, 3D cameras, and fluorescence lifetime imaging microscopy. With a single GRO serving as both the quantizer and residue generator, the GRO period can serve as the time reference to achieve intrinsic coarse-fine conversion. The proposed cyclic TDC also features a phase domain reset scheme which generates a compensation pulse for purging the GRO phase residue among consecutive conversion cycles. Fabricated in 65nm CMOS, this work occupied an area of 0.013mm2. The proposed TDC achieves a high resolution of 3.1ps together with an extended input range of 3.2ns. Consuming 1.41mW at 36MS/s from a 1-V supply, it also demonstrates a measured DNL and INL of +0.5/-0.6LSB and +3.3/-3.6LSB, respectively.

This article presents an auto-calibration technique for current-based bandgap voltage references (BGRs), based on a digitally-assisted auto-calibration loop for calibration cost reduction. We first present a theoretical study of the process variation induced $V_{\mathrm{EB}}$ and $\Delta V_{\text {EB}}$ variations in the BJT, which contribute to residual errors in the reference voltage ( $V_{\mathrm{REF}}$ ) and its temperature coefficient (TC) after applying conventional one-point trimming. Based on the study, we further propose an automatic one-point trimming methodology using a current digital-to-analog converter (IDAC), which can simultaneously relax the $A{V}$ EBand $\Delta V_{\mathrm{EB}}$ variations, resulting in a small drift in both $V_{\mathrm{REF}}$ and its TC after calibration. Fabricated in 65 nm standard CMOS, the proposed auto-calibrated BGR achieves a measured TC of 22.3 ppm/°C at 1.2 V supply within −40 °C to 120 °C. The line regulation is 1.26 mV/V or 0.13%/V from 1.2 to 2.5 V. Based on ten-chip measurement results, the achieved $\sigma /\mu $ variation in $V_{\mathrm{REF}}$ improves from ±0.53% to ±0.12% within the entire temperature spectrum after applying the proposed auto-calibration technique at 27 °C.

This article presents an efficient buck converter design using the proposed outphase-interleaved hybrid switched-capacitor (OISC) topology. The outphase-interleaved switched-capacitor (SC) cells significantly extend the $C_{\mathrm {F}}$ charge-balancing phase without disturbing the inductor volt-second balance (VSB), while doubling the effective inductor switching frequency for reduced current ripple. As a result, it addresses the intrinsic issue of sharply increased flying capacitor ( $C_{\mathrm {F}}$ ) inrush current in existing SC dual-/multi-path (DP/MP) hybrid buck converters under extreme duty ratios, resolving the tradeoff between SC cell conduction loss and inductor dc current ( $I_{L,\mathrm {dc}}$ ) reduction capability. The proposed topology attains three key advantages: 1) relived $C_{\mathrm {F}}$ hard-charging-induced inrush current; 2) reduced $I_{L,\mathrm {dc}}$ ; and 3) power stage normal operation without relying on an output capacitor $(C_{\mathrm {OUT}})$ , resulting in improved conversion efficiency and power density. To enhance the overall power density and mitigate gate-driving path ringing, we propose an area-efficient fully ON-chip gate-driving scheme with a shared charge pump (CP), ensuring proper operations with all-NMOS power switches. Fabricated in a 180-nm CMOS process with 7.63 mm2 chip area, the converter achieves a peak conversion efficiency of 97.3% and an overall peak current density of 585 mA/mm3 at 90.1% efficiency. Supporting a load current ( $I_{\mathrm {LOAD}}$ ) from 0.05 to 3.1 A, it converts 1.8–3.3 V input to 0.8–1.8 V output. Measured output voltage ( $V_{\mathrm {OUT}}$ ) ripple is ~3.3% of $V_{\mathrm {OUT}}$ dc under 3.1 A $I_{\mathrm {LOAD}}$ with zero $C_{\mathrm {OUT}}$ .

This brief presents a one cycle startup relaxation oscillator (RO) suitable for resource-constrained wearable and implantable applications. For improving energy efficiency without relying on a low supply voltage, we propose a self-synchronized power gating technique to completely shut down almost all the analog building blocks except near the clock toggling moment. We further relax the system startup energy and size by introducing the ratiometric threshold-referenced technique and deadlock avoidance circuit to quickly pre-bias the internal RC network without using extra on-chip references. The proposed RO is designed and fabricated in standard 0.18- $\mu \text{m}$ CMOS, with four distinct implementations at 1kHz, 10kHz, 100kHz, and 1MHz. Measurement results show that all the ROs can achieve one-cycle startup operation. The 100kHz RO, which occupies an active area of only 0.041mm2, achieves a line sensitivity of ±1.14%/V from 1.7 to 1.9V while exhibiting an energy efficiency of 2.7nW/kHz. After trimming on-chip resistors with complementary temperature coefficients (TCs), the 1MHz RO attains a measured TC of 82ppm/°C from–25 to 100°C, as well as a noise-power figure-of-merit (FoM) of 149 dBc/Hz@100kHz.

This letter presents a high-power-density point-of-load dc–dc converter for 12/24 V input applications, using the proposed high voltage-low voltage separated hybrid switched-capacitor (SC) topology. By incorporating inductors between the SC networks in HV/LV domains, the design achieves reduced inductor dc current (IL,DC) at small voltage conversion ratios (VCRs), optimized switching and conduction losses, and extended duty ratio range, enabling the use of small-sized inductors with higher dc resistance and resulting in a compact system volume. LV switches handle most of the current conduction, reducing switching losses and silicon area for higher on-chip power density. The fabricated converter, using a 180-nm BCD process, generates 0.8–1.8 V output from 12/24 V inputs with a 3-A maximum load. Measured results show total IL,DC of 1.2 A at VCR 0.075 and 2 A load. The converter achieves a peak power density of 355 mW/mm3 with a power passive volume of 15.2 mm3. Peak efficiencies are 85% at 12 V input and 84.2% at 24 V input.

This work proposes a high-step-down switched-capacitor (SC) hybrid DC-DC converter that effectively addresses the conduction loss in the inductor and power switches. Specifically, an architecture combining a dual-path hybrid (DPH) converter at the input, and a continuous-current-input SC (CISC) stage at the output, achieves superior performance in reducing the inductor DC current ( $I_{\mathrm {L,DC}}$ ) compared to the existing single-inductor two-flying-capacitor ( $1L$ - $2C_{\mathrm {F}}$ ) converters. Also, the converter exploits low-voltage (LV) switches to handle a substantial portion of the current, diminishing the reliance on the inductor or high-voltage (HV) switches. Consequently, this approach enhances the efficiency and on-chip power/current density. The converter, implemented in 180-nm BCD, integrates monolithic power switches, drivers, and control circuitry. It is capable of regulating an output voltage within the range of 1.2 to 3.5 V, accommodating a 12 V/24 V-input. The peak efficiency is 93% and the on-chip current density is 0.638A/mm2. The load current delivery is up to 3 A, even using a compact inductor with a DC resistance (DCR) of 200 $\text{m}\Omega $ .