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Single-phase ac to dc converters for computers and related applications have requirements that are difficult to meet while achieving both high power density and high efficiency: wide input voltage range, large voltage step down, galvanic isolation, harmonic current limits and hold-up requirements. This work explores a circuit architecture and topology that seeks to address this challenge, and presents a 250 W, 24 V output, universal input PFC converter prototype achieving 34.9 W/in3. The converter operates at variable switching frequencies in the range of 1-4 MHz; the measured efficiency at 230 Vac RMS, 60 Hz input is 95.33% at full load and 84.57% at 8% load.

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016., Cataloged from PDF version of thesis., Includes bibliographical references (pages 145-151)., With the present ac-voltage distribution system, ac-dc converters are key components for driving many dc voltage applications from the ac grid voltage. There are a lot of electronic devices that natively operate from the dc voltage including light emitting diodes (LEDs), personal and laptop computers, and smart phones; for all of them there is a drive to increase functionality and to reduce the volume at the same time. The desire for further miniaturization is, however, facing a dominant obstacle strained by the performance requirements on power electronic circuits. In this thesis, a design technique for high-performance ac-dc power converters will be presented. A new grid interface ac-dc conversion architecture and associated circuit implementations are proposed along with novel control methods. This approach simultaneously address design challenges associated with high performance (e.g., high efficiency, high power factor, miniaturization, and high reliability/lifetime) of ac-dc power conversion systems. The proposed architecture is suitable for realizing ac-dc converters that switch in the HF range (3-30 MHz) with relatively low-voltage components and with zero-voltage switching (ZVS) conditions, enabling significant converter size reduction while maintaining high efficiency. Moreover, the proposed approach can achieve reasonably high power factor about 0.9, while dynamically buffering twice-line frequency energy using small capacitors operating with large voltage swings over the ac line voltage cycle. The ac-dc converter design shows that excellent combinations of power density, efficiency, and power factor can be realized with this approach., by Seungbum Lim., Ph. D.

The design of power magnetic components for operation at high frequency (HF, 3–30MHz) has been hindered by a lack of performance data and by the limited design theory in that frequency range. To address these deficiencies, we have measured and present core loss data for a variety of commercially available magnetic materials in the HF range. In addition, we extend the theory of performance factor for appropriate use in HF design. Since magnetic materials suitable for HF applications tend to have low permeability, we also consider the impact of low permeability on design. We conclude that, with appropriate material selection and design, increased frequencies can continue to yield improved power density well into the HF regime., MIT Energy Initiative (Lockheed Martin), Texas Instruments Incorporated

This paper presents a merged-two-stage circuit topology suitable for either wide-range dc input voltage or ac line voltage at low-to-moderate power levels (e.g., up to 30 W). This two-stage topology is based on a soft-charged switched-capacitor preregulator/transformation stage and a high-frequency magnetic regulator stage. Soft charging of the switched capacitor circuit, zero voltage switching of the high-frequency regulator circuit, and time-based indirect current control are used to maintain high efficiency, high power density, and high power factor. The proposed architecture is applied to an LED driver circuit, and two implementations are demonstrated: a wide input voltage range dc-dc converter and a line interfaced ac-dc converter. The dc-dc converter shows 88%-96% efficiency at 30-W power across 25-200-V input voltage range, and the ac-dc converter achieves 88% efficiency with 0.93 power factor at 8.4-W average power. Contributions of this paper include: 1) demonstrating the value of a merged two-stage architecture to provide substantial design benefits in high-input voltage, low-power step down conversion applications, including both wide-range-input dc-dc and line-input ac-dc systems; 2) introduction of a multimode soft-charged SC stage for the merged architecture that enables compression of an 8:1 input voltage range into a 2:1 intermediate range, along with its implementation, loss considerations, and driving methods; and 3) merging of this topology with an resonant transition discontinuous-mode inverted buck stage and pseudocurrent control to enable step-down power conversion (e.g., for LED lighting) operating at greatly increased frequencies and reduced magnetics size than with more conventional approaches.

This paper presents a novel ac-dc power factor correction (PFC) power conversion architecture for single-phase grid interface. The proposed architecture has significant advantages for achieving high efficiency, good power factor, and converter miniaturization, especially in low-to-medium power applications. The architecture enables twice-line-frequency energy to be buffered at high voltage with a large voltage swing, enabling reduction in the energy buffer capacitor size, and elimination of electrolytic capacitors. While this architecture can be beneficial with a variety of converter topologies, it is especially suited for system miniaturization by enabling designs that operate at high frequency (HF, 3 – 30 MHz). Moreover, we introduce circuit implementations that provide efficient operation in this range. The proposed approach is demonstrated for an LED driver converter operating at a (variable) HF switching frequency (3 – 10 MHz) from 120Vac, and supplying a 35Vdc output at up to 30W. The prototype converter achieves high efficiency (92%) and power factor (0.89), and maintains good performance over a wide load range. Owing to architecture and HF operation, the prototype achieves a high ‘box’ power density of 50W/ in3 (‘displacement’ power density of 130W/ in3), with miniaturized inductors, ceramic energy buffer capacitors, and a small-volume EMI filter., United States. Advanced Research Projects Agency-Energy. Agile Delivery of Electrical Power Technology, Texas Instruments Incorporated

This paper presents a new power conversion architecture for single-phase grid interface. The proposed architecture is suitable for realizing miniaturized ac-dc converters operating at high frequencies (HF, above 3 MHz) and high power factor, without the need for electrolytic capacitors. It comprises of a line-frequency rectifier, a stack of capacitors, a set of regulating converters, and a power combining converter (or set of power combining converters). The regulating converters have inputs connected to capacitors on the capacitor stack, and provide regulated outputs while also achieving high power factor, with twice-line-frequency energy buffered on the capacitor stack. The power combining converter combines power from the individual regulated outputs to a single output, and may also provide isolation. While this architecture can be utilized with a variety of circuit topologies, it is especially suited for systems operating at HF (above 3 MHz), and we introduce circuit implementations that enable efficient operation in this range. The proposed approach is demonstrated for an LED driver operating from 120 V[subscript ac], and supplying a 35 V, 30 W output. The prototype converter operates at a (variable) switching frequency of 5-10 MHz and an efficiency of > 93%. The converter achieves a displacement power density of 130 W/in[superscript 3], while providing a 0.89 power factor, without the use of electrolytic capacitors.

This paper presents a merged-two-stage circuit topology suitable for efficient LED drivers operating from either wide-range dc input voltage or ac line voltage. This two-stage topology is based on a soft-charged switched-capacitor pre-regulator/transformation stage and a high-frequency magnetic regulator stage. Soft charging of the switched capacitor circuit, zero voltage switching of the high-frequency regulator circuit, and time-based indirect scale current control are used to maintain high efficiency, high power density, and high power factor. Two implementations of the proposed architecture are demonstrated: a wide input voltage range dc-dc converter and a line interfaced ac-dc converter. The dc-dc converter shows 85–95% efficiency at 20 W power across 25–200 V input voltage range, and the ac-dc converter achieves 88% efficiency with 0.93 power factor at 8.4 W average power.

The PowerChip research program is developing technologies to radically improve the size, integration, and performance of power electronics operating at up to grid-scale voltages (e.g., up to 200V) and low-to-moderate power levels (e.g., up to 50W) and demonstrating the technologies in a high-efficiency light-emitting diode driver, as an example application. This paper presents an overview of the program and of the progress toward meeting the program goals. Key program aspects and progress in advanced nitride power devices and device reliability, integrated high-frequency magnetics and magnetic materials, and high-frequency converter architectures are summarized.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012., Cataloged from PDF version of thesis., Includes bibliographical references (p. 71)., In a power converter specified to convert from wide-range and high-level DC voltage or AC line voltage to low-level DC voltage, satisfying high efficiency, high power density, and high power factor is challenging because of the higher device stress and difficulty of maintaining ZVS/ZCS conditions. Our purpose of the proposed two-stage power conversion architecture is to manage this high peak voltage stress and widely-varying operating conditions and to reduce dissipation by placing a switched capacitor pre-regulator stage in front of a very high frequency DC-DC converter stage. Our proposed two-stage architecture has been designed, built, and tested., by Seungbum Lim., S.M.