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This article presents a wide-lock-in-range and ultralow-jitter, 12–14.5 GHz subsampling phase-locked loop (SSPLL) using a frequency-disturbance-detecting/correcting (FDC) loop. By detecting and correcting the frequency disturbance, $f_{\mathbf {D}}$ , frequently, the FDC loop can increase the lock-in range of the SSPLL to 3.2 times the reference frequency, $f_{\mathbf {REF}}$. Since the FDC loop only is concerned with correcting an $f_{\mathbf {D}}$ -event at the output and is not concerned with the jitter, there is no design tradeoff between the jitter, and the power consumption as is the case in previous techniques. Due to its logic using frequency information rather than phase, the FDC loop also can reduce the time required for the reacquisition of the frequency. In this work, the prototype SSPLL was fabricated in a 65 nm CMOS, and it used the 50 MHz $f_{\mathbf {REF}}$. In the measurements, the FDC loop that consumed only 150 $\mu \text{W}$ of power made the SSPLL achieve the lock-in range of 160 MHz and the frequency-reacquisition time of less than 800 ns. The measured rms jitter at 13 GHz was 83 fs. The active area was 0.23 mm2, and the total power consumption was 7.7 mW. [ABSTRACT FROM AUTHOR]

This paper presents a 680 MHz–6 GHz $2 \times 2$ multiple-input and multiple-output (MIMO) long-term evolution (LTE) RF transceiver in 65-nm CMOS for low-cost and multi-band capable femtocell base stations. The transceiver integrates two receivers (RXs), two transmitters (TXs), and two frequency synthesizers, for the $2 \times 2$ MIMO operation to support both the frequency division duplex (FDD) and the time division duplex (TDD) modes. Each pair of an RX and a TX features eight single-ended low noise amplifiers (LNAs), and eight TX outputs that extensively share active and passive circuits with minimal performance degradation. In the measurement, each RX illustrates the noise figure (NF) from 2.9 to 5.2 dB, the input-referred third-order intercept point (IIP3) of more than −2 dBm, and the IIP2 of more than 48 dBm, over the entire frequency range at the maximum gain. Each TX achieved the adjacent channel leakage ratio (ACLR) that was less than −54 dBc at −5-dBm output power with −157-dBc/Hz phase noise at the RX band, while achieving an error-vector-magnitude (EVM) of less than 2.8%, over the entire frequency range. The transceiver, packaged in a flip-chip chip-scale package (fcCSP), is mounted on the board of the commercial femtocell of the LTE Band5, along with a commercial duplexer, power amplifier, and modem. The femtocell achieved −100-dBm reference sensitivity without the use of an external LNA. It also achieved −51-dBc TX ACLR and 1.68% TX EVM at 20-dBm output power in the LTE 10-MHz mode with the $2 \times 2$ MIMO configuration, without applying a digital pre-distortion (DPD) technique. [ABSTRACT FROM AUTHOR]

A wideband and low phase noise quadrature local oscillation (LO) signal generator for multistandard cellular transceivers was proposed. Using the new LO-plan consisting of divide-by-6, divide-by-4, and divide-by-12 frequency dividers, the required frequency-tuning range (FTR) of a voltage-controlled oscillator (VCO) was reduced to 39%, which can be easily covered by a single LC-VCO. Due to the reduced FTR, the VCO can retain a high Q-factor and achieve low phase noise. The key building block of the new LO-plan is a quadrature divide-by-6 divider, capable of generating precise I/Q signals. To implement the quadrature divide-by-6 divider, we proposed a fully differential divide-by-3 divider with 50% duty cycle. Using the same idea, a fully differential divide-by-2 circuit was also proposed for divide-by-4 and divide-by-12 dividers. The proposed LO-generator was fabricated in a 40 nm CMOS process, and covered LO-frequencies of 0.56–2.92 GHz for multistandard cellular transceivers. The LO-generator occupied a small silicon area of 0.15\;\textmm^2 and achieved an excellent phase noise performance of - 141.02\;\textdBc/\textHz at a 1 MHz offset from a 709 MHz LO-frequency. [ABSTRACT FROM PUBLISHER]