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Your search keyword '"Pott, Vincent"' showing total 30 results
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30 results on '"Pott, Vincent"'

2. Design, modeling and simulation of an anchorless nano-electro- mechanical nonvolatile memory

Author

Vaddi, Ramesh, Pott, Vincent, Lin, Julius Tsai Ming, Kim, Tony Tae-Hyoung, School of Electrical and Electronic Engineering, and International Conference on Solid-State and Integrated Circuit (2012 : Xi'an, China)

Subjects
Engineering::Electrical and electronic engineering::Microelectromechanical systems [DRNTU]
Abstract

Non Volatile Memories (NVMs) based on a storage layer, like FLASH, suffer from poor retention at high temperature, high voltage writing, and wear out while cycling. This paper presents the structure, operation and modeling details of a new NVM based on nano-electromechanical memory (NEM) cell having two stable mechanical positions and actuated by electrostatic forces. Permanent retention is obtained by adhesion forces only, eliminating the leakage observed in all types of storage layers. First part of the work focus on the introduction of single cell of NEM based NVM structure and operation. The second part of the work focus on NEM based NVM modeling and behavior implementation with Verilog-A compact modeling and testing in Cadence environment. The results verify the correct functionality and scalability of the new NEM cell. With the anchorless shuttle, the design is highly eased and scalable, compared to standard anchor based NEM structures. Published version

Published
2012

3. Demonstration of Integrated Mico-Electro-Mechanical Switch Circuits for VLSI Applications

Author

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science, Stojanovic, Vladimir Marko, Chen, Fred Fu-Chin, Fariborzi, Hossein, Spencer, Matthew, Nathanael, Rhesa, Wang, Chengcheng, Gupta, Abhinav, Kam, Hei, Pott, Vincent, Jeon, Jaeseok, Liu, Tsu-Jae King, Markovic, Dejan, Alon, Elad, Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science, Stojanovic, Vladimir Marko, Chen, Fred Fu-Chin, Fariborzi, Hossein, Spencer, Matthew, Nathanael, Rhesa, Wang, Chengcheng, Gupta, Abhinav, Kam, Hei, Pott, Vincent, Jeon, Jaeseok, Liu, Tsu-Jae King, Markovic, Dejan, and Alon, Elad

Abstract

A testchip demonstrates monolithic integration of micro-electro-mechanical (MEM) switch circuit building blocks for logic, timing, I/O and memory functions. Experimental results show functionality for an inverter, XOR, carry-generation block, oscillator, DAC, latch, and 10-cell DRAM., National Science Foundation (U.S.) (Infrastructure Grant No. 0403427), United States. Defense Advanced Research Projects Agency, Semiconductor Research Corporation. Center for Materials, Structures and Devices, Semiconductor Research Corporation. Center for Circuit and System Solutions, Berkeley Wireless Research Center

Published
2011

11. Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications

Author

Spencer, Matthew, primary, Chen, Fred, additional, Wang, Cheng C., additional, Nathanael, Rhesa, additional, Fariborzi, Hossein, additional, Gupta, Abhinav, additional, Kam, Hei, additional, Pott, Vincent, additional, Jeon, Jaeseok, additional, Liu, Tsu-Jae King, additional, Markovic, Dejan, additional, Alon, Elad, additional, and Stojanovic, Vladimir, additional

Published
2011
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16. Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications

Author

Chen, Fred, primary, Spencer, Matthew, additional, Nathanael, Rhesa, additional, Wang, Chengcheng, additional, Fariborzi, Hossein, additional, Gupta, Abhinav, additional, Kam, Hei, additional, Pott, Vincent, additional, Jeon, Jaeseok, additional, Liu, Tsu-Jae King, additional, Markovic, Dejan, additional, Stojanovic, Vladimir, additional, and Alon, Elad, additional

Published
2010
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26. Seesaw Relay Logic and Memory Circuits.

Author

Jaeseok Jeon, Pott, Vincent, Hei Kam, Nathanael, Rhesa, Alon, Elad, and Tsu-Jae King Liu

Subjects
*LOGIC circuits, *TRANSISTORS, *COMPUTER circuits, *DIGITAL electronics, *SWITCHING circuits
Abstract

Various logic functions can be implemented by appropriately biasing a single seesaw relay. The seesaw relay can also be configured as a bistable latch so that a memory cell can be implemented with one relay and one access transistor. Measurements of seesaw relay switching speed are well matched to lumped-parameter modeling results. [ABSTRACT FROM AUTHOR]

Published
2010
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27. Four-Terminal-Relay Body-Biasing Schemes for Complementary Logic Circuits.

Author

Nathanael, Rhesa, Pott, Vincent, Hei Kam, Jaeseok Jeon, Alon, Elad, and Tsu-Jae King Liu

Subjects
INTEGRATED circuits, MICROELECTROMECHANICAL systems, ELECTRONIC noise, HYSTERESIS, RELAY control systems, ELECTRIC relays
Abstract

Four-terminal-relay inverter circuit characteristics are investigated. To achieve maximum noise margin and zero crowbar current while allowing for relay-to-relay variations, the optimal biasing scheme provides for switching that is symmetric about VDD/2 with minimum hysteresis and no possibility of both the pull-down and pull-up devices being on simultaneously. [ABSTRACT FROM AUTHOR]

Published
2010
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28. Four-Terminal Relay Design for Improved Body Effect.

Author

Jaeseok Jeon, Nathanael, Rhesa, Pott, Vincent, and Tsu-Jae King Liu

Subjects
ELECTRIC relays, ELECTRIC potential, NANOELECTROMECHANICAL systems, ELECTRIC switchgear, NANOELECTRONICS
Abstract

Previously reported electrostatically actuated four-terminal (4T) relays suffer from a relatively weak body bias effect and undesirable influence of source/drain bias voltages on gate switching voltages. In this letter, an improved 4T relay design is demonstrated to resolve these issues. [ABSTRACT FROM AUTHOR]

Published
2010
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29. Perfectly Complementary Relay Design for Digital Logic Applications.

Author

Jaeseok Jeon, Pott, Vincent, Hei Kam, Nathanael, Rhesa, Alon, Elad, and Tsu-Jae King Liu

Subjects
ELECTRIC relays design & construction, LOGIC design, SWITCHING theory, MICROELECTROMECHANICAL systems, NANOELECTROMECHANICAL systems
Abstract

A dual-ended ("seesaw") relay design is proposed for ultralow-power digital logic applications. Fabricated seesaw relays demonstrate a perfectly complementary switching behavior that is symmetric about VDD/2, with extremely steep switching behavior (< 0.1 mV/dec) and low ON-state resistance (< 1 kΩ). The perfectly complementary and symmetric operation provides for maximum operating voltage margin and minimal crowbar current, as evidenced by an abrupt inverter voltage transfer characteristic. [ABSTRACT FROM AUTHOR]

Published
2010
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30. Hybrid SETMOS Architecture With Coulomb Blockade Oscillations and High Current Drive.

Author

Ionescu, Adrian Mihai, Mahapata, Santanu, and Pott, Vincent

Subjects
METAL oxide semiconductor field-effect transistors, FIELD-effect transistors, METAL oxide semiconductors, SEMICONDUCTORS, TRANSISTORS, ELECTRONICS
Abstract

A novel hybrid single electron transistor/MOSFET (SETMOS) circuit cell architecture, working as a three-terminal stand-alone device for obtaining SET-like Coulomb Blockade osdilations, along with a high current drive (∼ µA), is proposed. SETMOS characteristics are successfully predicted by analytical models at subambient (-100 °C to -150 °C) temperature with realistic device parameters. The effect of bias voltages and current on the SETMOS Coulomb Blockade oscillations characteristics is critically discussed. It is also demonstrated that the SETMOS can be converted into a unique quasi-periodic negative differential resistance (NDR) device by short-circuiting its gate and drain terminals. [ABSTRACT FROM AUTHOR]

Published
2004
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