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Approximate computing (AC) is an emerging technique in arithmetic circuits. In this letter, a new AC-based full adder (FA) circuit is presented with 12 transistors, 150mm]Please confirm or add details for any funding or financial support for the research of this article. -160mm]If you haven’t done so already, please make sure you have submitted a video graphical abstract (GA) for your paper, along with a caption and overlay image. The GA will be displayed on your articles abstract page on IEEE Xplore. Note that captions cannot exceed 1800 characters (including spaces). Overlay images are usually a screenshot of your video that best represents the video. This is for readers who may not have access to video-viewing software. 0.239 $\mu \text{m}^{2}$ of area, and two errors in the outputs. In the proposed FA, the gate diffusion input (GDI) and dynamic-threshold (DT) techniques are applied using the carbon nanotube field-effect transistor (CNTFET) technology. Accuracy metrics, such as normalized mean error distance (NMED) and mean relative error distance (MRED) along with circuitry parameters of power-delay-product (PDP), energy-delay-product (EDP), and power-delay-area-product (PDAP), confirm the efficiency of the proposed FA for complex structures. The proposed FA is embedded in a ripple carry adder (RCA) by various numbers of approximate bits (NABs), and then the accuracy and circuitry parameters are extracted. Compared to the state-of-the-art designs, the high-efficient behavior of the proposed FA is proved when it is used in image processing applications. [ABSTRACT FROM AUTHOR]

A new low‐power and high‐speed multiplier is presented based on the voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. The VOS reduces power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier. Hence, the proposed counters are implemented by the gate‐diffusion input technique to solve the speed limitation of the VOS‐based circuits. The proposed GDI‐based 5:3 and 7:3 counters save power and reduce the area by 2x and 2.5x, respectively. To prevent the threshold voltage (Vth) drop in the suggested GDI‐based circuits, carbon nanotube field‐effect transistor (CNTFET) technology is used. In the counters, the chirality vector and tubes of the CNTFETs are properly adjusted to attain full‐swing outputs with high driving capability. Also, their validation against heat distribution under different time intervals, as a major issue in the CNTFET technology is investigated, and their very low sensitivity is confirmed. The low complexity, high stability and efficient performance of the presented counter cells introduce the proposed VOS‐CNTFET‐GDI‐based multiplier as an alternative to the previous designs. [ABSTRACT FROM AUTHOR]