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Feedback after the output filter has long been a desired feature for high-power switching (Class-D) amplifiers, as it mitigates the influence of the LC filter components on the frequency transfer function and on linearity, enabling lower component costs. However, it requires compensation of the LC filter to maintain loop stability. In the analog domain, this is difficult to combine with high loop-gain, as the design has to cope with variability in both the LC filter and in the loop-filter. In [1], multiple analog feedback loop-filters from before and after the output filter have been employed, but the loop-gain of the outer loop is only ∼10dB at 20kHz. Alternatively, digital filters have no variability in their coefficients and are well suited for programmable compensation of the output filter, optionally even adaptive. In [2] feasibility is shown of a single digital loop with full global feedback. However, to achieve this, a costly commercially available ADC with 2.5MHz bandwidth and 950mW power consumption was required, a drawback that so far has prevented further adoption. In this paper we present a 5-channel Class-D amplifier with integrated low-latency delta-sigma (ΔΣ) ADCs, each consuming only 30mW, for digital feedback after the output filter. With this system, more than 50dB loop-gain is obtained. THD+N is 0.004% over the full audio band, which is at least 10× better than [1] where data is only given at 1kHz.

Out-of-band noise (OBN) is troublesome in analog circuits that process the output of a noise-shaping audio DAC. It causes slewing in amplifiers and aliasing in sampling circuits like ADCs and class-D amplifiers. Nonlinearity in these circuits also causes cross-modulation of the OBN into the audio band. These mechanisms lead to a higher noise level and more distortion in the audio band. OBN also leads to interference in the LF and MF band, compromising e.g. AM radio reception. To avoid these problems, it is desired to reduce OBN power to below -60dBFS. An active low-pass filter after the DAC output can reduce the OBN power to acceptable levels, but this solution is expensive in terms of power consumption and chip area. A FIR-DAC approach implements a 1b PWM modulator, followed by a semi-digital low-pass FIR reconstruction filter. It achieves high-end audio performance with sufficiently low OBN, but the FIR structure costs area, adds latency, and (like an analog low-pass filter) inherently limits the maximum output signal frequency. Multi-bit noise shapers employ smaller quantization steps and therefore output lower OBN. A cascaded-modulator architecture can directly be followed by an on-chip amplifier without low-pass filtering. However, with only 330 quantization levels, it still cannot achieve the desired -60dBFS OBN without additional filtering. Moreover, this approach requires complex dynamic-element matching (DEM) and inter-symbol interference (ISI) shaping mechanisms. The paper present an approach that reduces OBN to below -60dBFS with minimal increase in power and area consumption. It consists of two paths . The main path is based on the work of van Tuijl et al. (2004), containing a 128× oversampled 5b 3rd-order noise shaper, thermometer decoder and real-time DEM algorithm followed by a current DAC. Since the digital noise shaper generates negligible in-band noise products, the error signal of the noise shaper is practically equal to the OBN. This err- r signal is integrated (as part of the loop filter), quantized and fed to a correction path with a differentiating DAC (DIFF-DAC). This DAC inverts the integration action, obtaining unity signal transfer. The output currents of both paths are subtracted, reducing OBN significantly. Quantization noise of the correction path is shaped because the error signal is differentiated after quantization. Depending on the shape of the noise transfer function of the main DAC, the DIFF-DAC needs an over-range in order to accommodate the increased signal swing caused by the integration action. Still, area and power cost is minimal because the range of the DIFF-DAC is still only a fraction of the main DAC range.

On-chip data communication is an active research area, as interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Especially for global interconnects that have to span large parts of a chip, there is an increasing gap between transistor speed and interconnect bandwidth. To alleviate this problem, improvements in technology, architectures and circuits are needed. On the technology side, low-k dielectrics and reverse scaling can improve the interconnect behavior. On the architecture side, Network on chips (NoCs) can reduce the number of global interconnects. On the circuit side, which is the focus area of this thesis, more advanced strategies than the classical repeater insertion can be used to reduce the power consumption and increase the communication speed. In the thesis, it is shown that the bandwidth of interconnects is either limited by their distributed RC behavior (for long interconnects), or by the skin-effect. In both cases, the bandwidth is proportional to the cross-sectional area and inversely proportional to the length squared. The aggregate bandwidth per cross-sectional area can be optimized by choosing all cross-sectional dimensions roughly equal. The bandwidth of a single interconnect can be increased by using resistive (or resistive-inductive) receiver termination or capacitive transmitter termination. The crosstalk can be mitigated with twisted differential interconnects, where the number of twists determines for how many neighbors the crosstalk can be cancelled. With the aid of a symbol response analysis method, it is shown that simple equalization schemes are very effective to boost the achievable data rate, more so than multi-level signaling or band-pass modulation. To validate the concepts two demonstrator ICs were developed, both using 10mm long interconnects. The first chip, in a 130nm CMOS process, showed that a combination of pulse-width pre-emphasis, twisted interconnects and low-ohmic receiver termination can boost the data rate to 3Gb/s/ch (at 2pJ/bit), while a conventional transceiver reached only 0.55Gb/s/ch. The second test-chip, in 90nm CMOS, showed that a combination of a capacitive transmitter and a low-power sense-amplifier with DFE at the receiver can reduce the energy consumption to 0.28pJ/bit (at 2Gb/s), much lower than competing designs. Circuit simulations show that a capacitive transmitter and a low-power sense amplifier can also be very effective as transceivers in a NoC, with data rates in excess of 9Gb/s (at 130fJ/transition) over 2mm interconnects. Multiple transceivers can be connected back-toback to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6σ offset reliability at 5 Gb/s

— A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a one-sigma offset of 8mV, the circuit consumes 92fJ/decision at 1.2V supply. It has an input equivalent noise of 1.5mV and requires only 18ps setup plus hold time.

—Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper a low-swing transceiver for 10mm long 0.54μm wide on-chip interconnect is presented, which achieves a similar data rate as previous designs (a few Gb/s), but at much lower power than recently published work. Both low static power and low dynamic power (low energy per bit) is aimed for. A capacitive pre-emphasis transmitter lowers the voltage swing and increases the bandwidth using a simple inverter based transceiver and capacitive coupling to the interconnect. The receiver uses Decision Feedback Equalization with a power-efficient continuous-time feedback filter. A low power latch-type voltage sense amplifier is used. The transceiver, fabricated in a 1.2V 90nm CMOS process, achieves 2Gb/s. It consumes only 0.28pJ/b, which is 7 times lower than earlier work.

A data converter comprises a discrete-time sigma delta modulator e.g. for driving a Class-D power amplifier. The low-pass filter of the sigma delta modulator is modified by adding a suitably positioned pole to lower the oscillation frequency (limit cycle) of the sigma delta modulator in order to obtain increased clustering of the pulses applied to the output of the data converter.

A centimetre may seem like nothing, but on a microchip it easily becomes an insurmountable distance. In order to transmit gigabits of data over this distance, Daniel Schinkel has had to pull out all the stops. Analog and digital technology come together in the Integrated Circuit Design group, which recently became part of the CTIT.

Global on-chip communication is receiving quite some attention as global interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Recently, we proposed a bus-transceiver test chip in 0.13 μm CMOS using 10 mm long uninterrupted differential interconnects of only 0.8 μm pitch. These small interconnects suffer from severe inter-symbol interference due to their high distributed resistance and capacitance. By using pulse-width equalization and low-ohmic termination, the inter-symbol interference is reduced and the achievable data rate is increased from 0.55 Gb/s/ch to 3 Gb/s/ch. Next to inter-symbol interference, the interconnects also suffer from crosstalk from neighboring interconnects. Analysis and measurements show that this crosstalk would impede the achievable data rate if it were not mitigated. In order to cancel the crosstalk, one twist is placed in every even interconnect in the bus and two twists are placed in every odd interconnect in the bus. Analysis shows that there are optimal positions for these twists, depending on the termination of the interconnects. Theory and measurements show that only one twist at 50% of the even interconnects, two twists at 30% and 70% of the odd interconnects and equal source and load impedances are very effective in mitigating the crosstalk.

Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper we show how a special form of equalization, pulse-width pre-emphasis, can significantly increase the data rate for a given length of uninterrupted interconnect, especially if used in combination with lowohmic termination and twisted differential interconnects. To validate these techniques, a bus-transceiver test chip in a 0.13μm, 1.2V, 6M copper CMOS process has been designed. The chip uses 10mm long differential interconnects with wire widths and spacing of only 0.4μm. With transceivers operating in conventional mode, the chip achieves only 0.55Gb/s/ch. The achievable data rate increases to 3Gb/s/ch (consuming 2pJ/bit) if pulse-width pre-emphasis and low-ohmic termination are turned on.

Global on-chip communication is rapidly becoming a speed and power bottleneck in CMOS circuits. In this paper, a ‘mixed-signal’ approach is taken to analyze on-chip interconnects and it is investigated how data-rates can be improved. It is shown that complex signaling schemes such as OFDM and CDMA are not efficient to improve the data-rate, while equalization can significantly improve the achievable data-rate. A combination of an equalizing transmitter with a low-ohmic receiver can improve the achievable data-rate by about a factor of 7.

This paper discusses a recursive multibit Σ∆ architecture that enables a high effective quantizer resolution while needing only a limited number of DAC elements. The recursive architecture consists of a set of Σ∆ modulators, whereby each stage cancels the quantization noise of the preceding stage. Conventional DEM algorithms can be used in each stage to reduce the sensitivity to mismatch. The architecture enables a significant reduction of both the signal-band and out-ofband quantization noise power, compared to conventional multibit Σ∆ converters.

A digital volume control device comprises a logic unit for volume control of digital input signals. Successively supplied m-bits words with maximally k bits active, derived from the output signals of or supplied by a volume control (4) with a quantizer (5) element the filtered m-bits workds are passed, however, with only the j most significant active bits of these filtered signals. The noise shaper operates with a frequency that is a k/j-fold of the frequency by which the m-bits words are supplied. An up-sampler (3) is provided for operation frequency adjustment of the filtered m-bits words to the noise shaper. This operation frequency is at least a factor k/j greater than the sample rate of the digital input signals. The control signals for the logic unit are formed by the m-bits words passed by the quantizer.

This paper introduces a recursive multibit ΣΔ architecture that enables a high effective quantizer resolution while needing only a limited number of DAC elements. The recursive architecture consists of a set of ΣΔ modulators, whereby each stage cancels the quantization noise of the preceding stage. Conventional DEM algorithms can be used in each stage to reduce the sensitivity to mismatch. The architecture enables a significant reduction of both the signal-band and out-of-band quantization noise power, compared to conventional multibit ΣΔ converters.

A CMOS temperature switch with uncalibrated high temperature accuracy is presented. The circuit is based on the classical CMOS bandgap reference structure, using parasitic PNPs and a PTAT multiplier. The circuit was designed in a standard digital 0.18 µm CMOS process. The temperature switch has a in-designed hysteresis of 1.2° C around a threshold value of 128° C. At the switching-threshold all matched transistors have also matched operating conditions, yielding a temperature threshold that is highly independent of transistor output resistance and supply voltage. With a chip area of only 0.03 mm2:, the on-wafer 3σ spread of the threshold temperature is 1.1° C. Power consumption is only 15 µA at 1 Volt supply.