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The low-voltage power capabilities of a low-cost high-performance silicon bipolar process were investigated. By optimizing the emitter finger layout, epilayer thickness, and collector doping level, efficiency values up to 83% were achieved by on-wafer load-pull measurements on a single-cell test device operating at 1.8 GHz and 2.7-V power supply. The detrimental effect of the emitter distributed resistance on the current capability of long-emitter bipolar transistors was also considered. An analytical model for a proper device design was derived and experimentally validated. Using the optimized unit power device, a 1.8-GHz 2.7-V three-stage monolithic power amplifier was implemented, which provides a 57% power-added efficiency and a 33-dB gain while delivering a 34-dBm output power to the load. Index Terms--DC current capability, mobile communications, RF power amplifier (PA), silicon bipolar technology.

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-μm 2.5-V standard 110 FETs in a 0.13-μm silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs. [ABSTRACT FROM AUTHOR]

A 5-GHz transmitter front-end for 802.11a and HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-fT silicon bipolar technology. The transmitter includes a digitally controlled linear-in-dB variable-gain up-converter and a three-stage linear power amplifier. At a 3-V supply voltage, the front-end exhibits a 23.5-dBm output 1-dB compression point, 35-dB maximum power gain, and 30-dB dynamic range. The dB-linear gain error is lower than ±0.8 dB. The transmitter is able to comply with the stringent error vector magnitude requirement of the standard up to a 19-dBm output power level. [ABSTRACT FROM AUTHOR]