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In this article, a new modulation scheme is proposed to minimize the device-level current stress in full-bridge submodule based modular multilevel converter (FBSM-MMC), operating under extended modulation. Unlike conventional methods, the proposed approach inserts submodules as a combination of positive and negative voltages. This unique strategy alters device loading patterns, effectively redistributing the root-mean squared (RMS) current throughout the submodules. A key advantage of this approach is the elimination of complex measurements or additional control strategies common in existing methods. Furthermore, this method avoids the drawbacks associated with adapting methods designed for half-bridge submodule based MMC. The proposed scheme also offers the advantage of lower overall losses as compared to conventional methods. This article presents detailed mathematical analysis of RMS currents in both conventional and proposed approaches. Finally, the theoretical findings are validated through a laboratory-scale experimental prototype.

The medium voltage (MV) high-power dc–dc isolated converter topologies are gaining huge interest as they offer high efficiency and power density. In the recent past, one of the major research areas for such system has been the reduction of rate of change of voltage ($dv/dt$) across the transformer windings and voltage stress across switches. This letter proposes a multiswitch-leg dual active bridge converter topology to reduce the $dv/dt$ across the transformer windings at high switching frequency (${{f}_s}$) operation. The proposed converter is scalable based on the MVdc-bus voltage and operates at simplest operating principle with zero circulating current. The proposed converter also features zero-voltage switching operation, which improves the efficiency. The operation of the proposed converter is verified by the experimental result of lab prototype.

Modular multilevel converter (MMC) is the most competitive topology for high and medium-voltage applications. It is known that any voltage mismatch between its phase legs causes a second-harmonic-dominant circulating current (CC) to flow in each of the MMC arms. This current, if not controlled properly, leads to reduced efficiency, larger energy storage requirements, and increased current rating of semiconductor switches. To address all these issues, a new CC control scheme is proposed in this paper, which is based on the principle of injecting a second-harmonic circulating current (SHCC) with a predefined magnitude and phase angle. A design methodology is presented to determine the desired magnitude and phase angle of the SHCC. In addition, a comparative study involving the proposed and other major CC control schemes is also presented to establish the main features of the proposed principles. Using the proposed control scheme, the overall energy storage requirement can be reduced by 30% without increasing the current rating of semiconductor switches. The efficacy of the proposed scheme is verified and comparatively evaluated using a 13-level, grid-connected simulation model and also using a 7-level, grid-connected MMC experimental setup.

The gate-driver circuits are required to control the switching dynamics of the power electronic (PE) devices. These gate drivers can be categorized as voltage-source drivers (VSDs) and current-source drivers (CSDs) based on their operating natures. The VSDs control the dynamics of the power device by means of an external gate resistor, which accounts for loss and it increases with switching frequency. On the other hand, CSDs with controlled gate current account for negligible loss and allow faster switching transition of the power device. This article provides a categorization of the prior-art CSDs based on their nature of operation and structural orientation. A comparative study is carried out between these CSDs based on the control switch count, switching frequency, and the passive components utilized. Furthermore, a case study of a representative CSD topology from each category is carried out and compared with the conventional VSD. An experimental setup for the double-pulse test is developed to prove the efficacy of CSD over VSD. It is observed that the power device when driven by CSD achieves lower turn-off and turn-on times compared to VSD by 75% and 50%, respectively. The effectiveness of CSDs for various applications is also highlighted in this article.

The hybrid series converter (HSC) has enhanced the operating modulation-index (MI) range compared to the parallel hybrid converter (PHC). However, the HSC is underutilized when employed for applications such as HVdc. The parallel chain links (PCLs) of the HSC generate rectified voltage of fixed amplitude, whereas the series chain links (SCLs) serve as voltage wave-shaping circuit. The maximum output voltage of the HSC is equal to the PCL rating. Moreover, HSC (and also PHC) demands three single-phase transformers for their operation and consists of series/director switches (DSs) that undergo high voltage and dv/dt stress. This article intends to extract all the advantages inherent with the HSC and utilize it to its maximum ability by restructuring and operating it as a transformer-less hybrid-series static compensator (THSSC). The SCLs of the THSSC act as a voltage-aiding circuit and reduce voltage stress across DSs. In addition, the THSSC has a lower energy storage requirement and requires fewer submodule capacitors and switching devices. During unbalanced grid conditions, capacitor voltages related to different phases of the THSSC tend to divert from reference. The required quantity of zero-sequence voltage (ZSV) is injected into the PCL and SCL of all three phases to govern capacitor voltages. The expression for reference ZSV is derived by using the feed-back and feed-forward methods. The converter's working principle and capacitor voltage control technique are authenticated using experimental results obtained under different grid voltage conditions.

This article presents a new hybrid multilevel converter for medium voltage dc–dc interconnection. The structure of the topology is a hybrid of two-level converter and the modular multilevel converter (MMC). The proposed converter provides three-phase trapezoidal output voltages with a controlled slope while using only a single MMC leg. Therefore, using fewer submodules and sensors, and with its feature of low energy storage requirement (ESR), the overall size of the converter reduces. The front-to-front configuration of the proposed converter provides the desired voltage matching, grounding flexibility, and dc fault blocking capability. Moreover, the phase leg switches and the bidirectional switches of the converter are operated in the soft switching mode reducing the converter losses. A detailed mathematical analysis is presented to substantiate the low ESR and losses of the proposed converter. The performance evaluation of the proposed dc–dc converter is carried out in PSCAD/EMTDC and analyzed in detail. The operation of the converter is also verified on a developed scaled-down laboratory prototype.