Search

Adiabatic quantum-flux-parametron (AQFP) logic is a proven energy-efficient superconductor technology for various applications. To address the scalability challenges, we investigated AQFP shift registers with the AQFP footprint area reduced by 25% with respect to prior work and with more than 2x denser overall designs obtained by eliminating the previously used free space between the AQFPs. We also investigated AQFP cells with different designs of flux trapping moats in the superconducting ground plane as well as compact AQFP cells that took advantage of the smaller feature sizes available in the new fabrication process, SFQ5ee+, at MIT Lincoln Laboratory. This new process features nine planarized Nb layers with a 0.25 $\mu$m minimum linewidth. The fabricated circuits were tested in a liquid He probe and in a closed-cycle cryocooler using a controlled cooling rate through the superconducting critical temperature. Using multiple thermal cycles, we investigated flux trapping in the dense AQFP shift registers as well as in the registers using the old (sparse) AQFP designs at two levels of the residual magnetic field, about 0.53 $\mu$T and about 1.2 $\mu$T. The sparse designs demonstrated 95% to almost 100% probability of operation after the cooldown and very wide operation margins, although the flux trapping probability was increasing with circuit complexities. The margins were similarly wide in the newer dense designs, but flux trapping probability that rendered the registers nonoperational was significantly, by an order of magnitude, higher in the denser circuits and was also very sensitive to the moats' shape and location. Our findings indicate that AQFP circuits are amendable to increasing the scale of integration and further densification, but a careful moat design and optimization are required to reduce flux trapping effects in the dense AQFP circuits., Comment: 5 pages, 10 figures, 2 tables, 18 references. Presented at Applied Superconductivity Conference, ASC2024, 1-6 September 2024, Salt Lake City, UT, USA

Moats in superconducting ground planes are used to trap magnetic flux away from sensitive parts of superconductor integrated circuits. We simulate the effect of magnetic flux trapped in moats on the operating margins of ac-biased SFQ shift registers (ShReg) with two ground planes for various congruent moat geometries, moat sizes, locations in the ShReg cells, number and polarity of the trapped of fluxons. Using inductance extractor InductEx, we extract mutual couplings between the moats and the ShReg inductors and include them in the refined netlist. Then, we use JoSim to simulate the circuit operation and find the threshold ac clock amplitude above which the register starts to operate correctly. The relative change in this threshold is used to characterize the influence of flux trapping on the circuit operation. Monte-Carlo simulations are used to investigate the effect of the circuit parameter variations on the statistics of the threshold, using the standard deviation of the Josephson junction critical current and of the circuit inductance extracted from the fabrication process control monitors. The obtained distributions are compared with the independently measured distributions of the threshold amplitude for the individual cells of ac-biased shift registers with 108,500 Josephson junctions. The results show that flux trapping in properly designs moats have a very small effect on the operation margins of the large-scale shift registers whereas the main contribution to the cell-to-cell variation of the threshold comes from the variation of the junctions' critical currents., Comment: 5 pages, 6 figures, 3 tables, 12 reference. Presented at Applied Superconductivity Conference ASC2024, 1-6 September 2024, Salt Lake City, UT, USA

To increase integration scale of superconductor electronics, we are developing a new, SFQ7ee, node of the fabrication process at MIT Lincoln Laboratory. In comparison to the existing SFQ5ee node, we increased the number of fully planarized superconducting layers to ten and utilized NbN and NbN/Nb kinetic inductors to increase the inductor number density above 100 million per cm$^2$. Increasing the Josephson junction (JJ) number density to the same level requires implementing self-shunted high-$J_c$ JJs. We investigated properties of Nb/NbN$_x$/Nb trilayer JJs as a potential replacement of high-$J_c$ Nb/Al-AlO$_x$/Nb JJs, where NbN$_x$ is a disordered, nonsuperconducting nitride deposited by reactive sputtering. Dependences of the $I_cR_n$ product and Josephson critical current density, $J_c$ on the NbN$_x$ barrier thickness and on temperature were studied in the thickness range from 5 nm to 20 nm. The fabricated JJs can be described by the microscopic theory of SNS junctions, assuming no suppression of the energy gap in Nb electrodes near the NbN$_x$ interfaces and a Cooper pair decay length in the NbN$_x$ barrier of about 2.3 nm. Current-voltage characteristics of the JJs are well described by the RCSJ model. In the studied range $J_c$ < 10 mA/$\mu$$m^2$, the Nb/NbN$_x$/Nb JJs have lower specific resistance $R_nA$, lower $I_cR_n$ product, and a stronger dependence of the $I_cR_n$ on temperature than self-shunted or critically damped externally shunted Nb/Al-AlO$_x$/Nb JJs with the same critical current density; here $A$ is the JJ area, $R_n$ the JJ effective shunting resistance., Comment: 8 pages, 7 figures, 55 references. Presented at EUCAS 2023, September 3-7, 2023, Bologna, Italy

To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of $10^8$ Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted Nb/Al-AlOx/Nb JJs and kinetic inductors. The process has a layer of JJs, a layer of resistors, and 10 fully planarized superconducting layers: 8 Nb layers and 2 layers of high kinetic inductance materials, Mo$_2$N and NbN, with sheet inductance of 8 pH/sq and 3 pH/sq, respectively. NbN films were deposited by two methods: with $T_c$=15.5 K by reactive sputtering of a Nb target in Ar+N$_2$ mixture; with $T_c$ in the range from 9 K to 13 K by plasma-enhanced chemical vapor deposition (PECVD) using Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of NbN was investigated to obtain conformal deposition and filling narrow trenches and vias with high depth-to-width ratios, which was not possible to achieve using sputtering and other physical vapor deposition (PVD) methods at temperatures below $200 ^oC$ required to prevent degradation of Nb/Al-AlOx/Nb junctions. Nb layers with 200 nm thickness are used in the process layer stack as ground planes to maintain a high level of interlayer shielding and low intralayer mutual coupling, for passive transmission lines with wave impedances matching impedances of JJs, typically <=50 $\Omega$, and for low-value inductors. NbN and NbN/Nb bilayer are used for cell inductors. Using NbN/Nb bilayers and individual pattering of both layers to form inductors allowed us to minimize parasitic kinetic inductance associated with interlayer vias and connections to JJs as well as to increase critical currents of the vias. Fabrication details and results of electrical characterization of NbN films, wires, and vias, and comparison with Nb properties are given., Comment: 12 pages, 16 figures, 4 tables, 49 references. Submitted to IEEE TAS on Nov. 10, 2022

Superconductor single flux quantum (SFQ) technology is attractive for neuromorphic computing due to low energy dissipation and high, potentially up to 100 GHz, clock rates. We have recently suggested a new family of bioSFQ circuits (V.K. Semenov et al., IEEE TAS, vol. 32, no. 4, 1400105, 2022) where information is stored as a value of current in a superconducting loop and transferred as a rate of SFQ pulses propagating between the loops. This approach, in the simplest case dealing with positive numbers, requires single-line transfer channels. In the more general case of bipolar numbers, it requires dual-rail transfer channels. To address this need, we have developed a new comparator with a dual-rail output. This comparator is an essential part of a bipolar multiplier that has been designed, fabricated, and tested. We discuss bioSFQ circuits for implementing an analog bipolar divide operation $Y/X$ and a square root operation $X^{1/2}$. We discuss strategic advantages of the suggested bioSFQ approach, e.g., an inherently asynchronous character of bioSFQ cells which do not require explicit clock signals. As a result, bioSFQ circuits are free of racing errors and tolerant to occasional collision of propagating SFQ pulses. This tolerance is due to stochastic nature of data signals generated by comparators operating within their gray zone. The circuits were fabricated in the eight-niobium-layer fabrication process SFQ5ee developed for superconductor electronics at MIT Lincoln Laboratory., Comment: 8 pages, 10 figures, 30 references. This paper was presented at Applied Superconductivity Conference, ASC 2022, October 23-28, 2022, Honolulu, Hawaii

We present measurements of the self- and mutual inductance of NbN and bilayer NbN/Nb inductors with Nb ground plane(s) fabricated in an advanced process for superconductor electronics developed at MIT Lincoln Laboratory. In this process, the signal traces of logic cell inductors are made either of a 200-nm NbN layer with $T_c$=15 K or of an in-situ deposited NbN/Nb bilayer, replacing a 200-nm Nb layer M6 in the standard SFQ5ee process with nine superconducting layers. Nb ground planes were preserved to maintain a high level of interlayer shielding and low intralayer mutual coupling. A two-step patterning of the top Nb and the bottom NbN layers of the NbN/Nb bilayer allows to create inductors in a very wide range of linear inductance values, from low values ~ 0.4 pH/$\mu$m typical for Nb geometrical inductors to ~ 35 pH/$\mu$m typical to thin-film kinetic inductors. Mutual inductance of NbN and Nb inductors, of NbN inductors, and of bilayer inductors is the same as between two Nb inductors with the same geometry and placement between the ground planes, i.e., mutual inductance does not depend on superconducting properties of the signal traces in the studied range of linewidths. We measured magnetic field penetration depth and kinetic inductance of NbN films with thickness t=200 nm to be $\lambda$ = 491+/-5 nm and 1.51 pH/sq, and 2.06 pH/sq at t=150 nm. The kinetic inductance was found to be larger than that expected for superconductors with short mean free path, indicating a reduction in the superfluid density, likely due to carrier localization effects. Kinetic inductance associated with right-angled bends of the NbN inductors is negligible at linewidths $w<{\lambda}^2/t$, indicating a very small current crowding in structures with superconducting ground plane(s). Implementation of NbN and NbN/Nb inductors can significantly increase integration scale of superconductor digital electronics., Comment: 11 pages, 9 figures, 4 tables, 60 references

Flux transformers are the necessary component of all superconductor digital integrated circuits utilizing ac power for logic cell excitation and clocking, and flux biasing, e.g., Adiabatic Quantum Flux Parametron (AQFP), Reciprocal Quantum Logic, superconducting sensor arrays, qubits, etc. We consider limitations to the integration scale (device number density) imposed by the critical current of the ac power transmission lines and cross coupling between the adjacent transformers. The former sets the minimum line width and the mutual coupling length in the transformer, whereas the latter sets the minimum spacing between the transformers. Decreasing linewidth of superconducting (Nb) wires increases kinetic inductance of the transformer's secondary, decreasing its length and mutual coupling to the primary. This limits the minimum size of transformers. As a result, there is a minimum linewidth ~100 nm which determines the maximum achievable scale of integration. Using AQFP circuits as an example, we calculate dependence of the AQFP number density on linewidth for various types of transformers and inductors available in the SFQ5ee fabrication process developed at MIT Lincoln Laboratory, and estimate the maximum circuit density as a few million AQFPs per cm^2. We propose an advanced fabrication process for a 10x increase in the density of AQFP and other ac-powered circuits. In this process, inductors are formed from a patterned bilayer of a geometrical inductance material (Nb) deposited over a layer of high kinetic inductance material (e.g., NbN). Individual pattering of the bilayer layers allows to create stripline inductors in a wide range of inductances, from the low values typical to Nb striplines to the high values typical for NbN thin films, and preserve sufficient mutual coupling in stripline transformers with extremely low crosstalk., Comment: 18 pages, 18 figures, 45 references

Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths of signal traces from 250 nm to a few micrometers, located on the same circuit layer at various distances from each other (from 250 nm to a few micrometers) and/or on different layers spaced vertically; effect of long slits in the ground plane(s) along the inductors on their mutual inductance; inductance of right-angled bends; inductance of meanders. Simple analytical expressions for mutual and self-inductance of the basic inductors are given, describing experimental data with accuracy better than 2% in a very wide range of parameters. They can be used for superconductor integrated circuit design and calibration of numerical inductance extractors. Measurements were done using circuits fabricated in fully planarized fabrication processes with eight niobium layers and Nb/Al-AlOx/Nb Josephson junctions, known as the SFQ5ee and SC1 processes developed at MIT Lincoln Laboratory for superconductor electronics. Mutual inductance decreases exponentially with distance between striplines and as a second power of the distance between microstrips, strongly depends on magnetic field penetration depths in superconducting ground planes, whereas superconducting properties of the signal traces are practically immaterial. Weak dependence of mutual inductance on the linewidth of superconducting wires indicates that area of superconducting flux transformers - the essential component of all digital circuits using ac power, superconducting qubits, and sensor arrays - scales poorly with the linewidth, putting a predictable upper limit on the integration scale of such circuits., Comment: 35 pages, 28 figures, 2 tables, 86 references

Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200 mm wafers at 4.4 K, including SQIF-based magnetic field sensors, SQUID-based circuits for measuring inductors, Nb/Al-AlOx/Nb Josephson junctions, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. Data on the wafer-scale distributions of the residual magnetic field, junction tunnel resistance, energy gap, inductance of multiple Nb layers, critical currents of interlayer vias are presented. Comparison with existing models is made. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory. The cryogenic wafer prober was developed at HPD/ FormFactor, Inc., Comment: 11 pages, 11 figures, 1 table, 27 references

Superconductor electronics (SCE) is competing to become a platform for efficient implementations of neuromorphic computing and deep learning algorithms (DLAs) with projects mostly concentrating on searching for gates that would better mimic behavior of real neurons. In contrast, we believe that most of the required components have already been demonstrated during the long history of SCE, whereas the missing part is how to organize these components to efficiently implement DLAs. We propose a family of logic/memory cells in which stored multi-bit data are encoded by quasi-analog currents or magnetic flux in superconductor loops while transmitted data are encoded as the rate of SFQ pulses. We designed, fabricated, and tested some of the basic cells to demonstrate a proof of concept, e.g., a unipolar and bipolar multipliers based on Josephson junction comparators. We coined the term bioSFQ to clearly connote close but distinguishable relations between the conventional SFQ electronics and its new neuromorphic paradigm., Comment: 6 pages, 6 figures, 29 references. Presented at 15-th European Conference on Applied Superconductivity, September 5-9, 2021, presentation #291

Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers and composite vias between distant superconducting layers. Effects of magnetic flux trapping in ground plane moats on coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations. Test circuits used for the measurements were fabricated in a new 150-nm node of a fully planarized process with eight niobium layers, SC2 process, developed at MIT Lincoln Laboratory for superconductor electronics and in its 250-nm node SC1, as well as in the standard fabrication process SFQ5ee. The SC2 process utilizes 193-nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. All other processes use 248 nm photolithography. Effects of variation of process parameters on circuit inductors are discussed. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Part II is devoted to mutual inductance of various closely spaced features in integrated circuits, meanders, and transformers., Comment: 21 pagers, 21 figures, 4 tables, 61 references. This work was presented at Applied Superconductivity Conference, ASC 2020 Virtual Conference, Oct. 24 - Nov. 7, 2020

Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per square centimeter. However, conventional DC and multi-phase AC biasing techniques already encounter serious challenges for scaling circuits above several hundred thousand junctions. In this work, we propose a novel AC-based biasing scheme for RSFQ-type logic families requiring DC bias. The major step toward this scheme is a superconducting AC/DC rectifier which we introduced at ASC 2014. Initially, we proposed to connect the rectifiers to 'payload cells' via superconducting inductors with large inductance in order to reduce parasitic effects of flux quantization. Recently, we discovered that this powering scheme works even better at a much lower value of the inductance, when it is just sufficient to hold only one or two flux quanta in the inductive loop between the converter and the payload. In this case, flux quantization in the loop becomes beneficial because the value of current fed into the payload is defined by the value of the coupling inductance. Therefore, our AC/SFQ converter powers the payload cell by a single flux quantum rather than by DC current. Such mode of operation is extremely energy efficient because the energy is used only to recover flux quantum consumed by the cell during the logic operation. We present designs of AC/SFQ converters comprising an AC/DC rectifier and a current conditioning circuit which we termed an SFQ filter. We also present test results and demonstrate AC/SFQ powering a payload circuit using circuits fabricated in a new, 150-nm node of Lincoln Laboratory fabrication technology using self-shunted Nb/AlOx-Al/Nb Josephson junctions with 600 $\mu$A/$\mu$$m^2$ critical current density and 200 nm minimum linewidth of inductors., Comment: 7 pages, 8 figures, 24 references. Presented at Applied Superconductivity Virtual Conference, ASC 2020, 24 October - 7 November 2020, https://ascinc.org

Arrays of Vortex Transitional (VT) memory cells with functional density up to $1 Mbit/cm^2$ have been designed, fabricated, and successfully demonstrated. This progress is due to recent advances in design optimization and in superconductor electronics fabrication achieved at MIT Lincoln Laboratory. As a starting point, we developed a demo array of VT cells for the 100-${\mu}A/{\mu}m^2$ MIT LL fabrication process SFQ5ee with 8 niobium layers. The studied two-junction memory cell with a two-junction nondestructive readout occupied $168 {\mu}m^2$, resulting in an over $0.5 Mbit/cm^2$ functional density. Then, we reduced the cell area down to $99 {\mu}m^2$ (corresponding to over $0.9 Mbit/cm^2$ functional density) by utilizing self-shunted Josephson Junctions (JJs) with critical current density, $J_c$ of $600 {\mu}A/{\mu}m^2$ and eliminating shunt resistors. The fabricated high-$J_c$ memory cells were fully operational and possessed wide Read/Write current margins, quite close to the theoretically predicted values. We discuss approaches to further increasing the integration scale of superconductor memory and logic circuits: a) miniaturization of superconducting transformers by using soft magnetic materials; b) reduction of JJ area by using planar high-$J_c$ junctions similar to variable thickness bridges., Comment: 9 pages, 10 figures, 1 Table, 49 references. Submitted to IEEE Transactions on Applied Superconductivity on October 30, 2018; in revised version on February 22, 2019. Presented at Applied Superconductivity Conference ASC 2018, 28 Oct.- 2 Nov. 2018, Seattle, WA, USA; paper 4EPo-1D

We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional Superconductor-Insulator-Superconductor (SIS) Nb/Al/AlO_x/Nb junctions with the same or different Josephson critical current densities, J_c. The process also allows integration of high-J_c Superconductor-Ferromagnet-Superconductor (SFS) or SFS'S JJs on the first junction layer with Nb/Al/AlO_x/Nb trilayer junctions on the second junction layer, or vice versa. In the present node, the SFS trilayer, Nb/Ni/Nb is placed below the standard SIS trilayer and separated by one niobium wiring layer. The main purpose of integrating the SFS and SIS junction layers is to provide compact {\pi}-phase shifters in logic cells of superconductor digital circuits and random access memories, and thereby increase the integration scale and functional density of superconductor electronics. The current node of the two-junction-layer process has six planarized niobium layers, two layers of resistors, and 350-nm minimum feature size. The target Josephson critical current densities for the SIS junctions are 100 {\mu}A/{\mu}m^2 and 200 {\mu}A/{\mu}m^2. We present the salient features of the new process, fabrication details, and characterization results on two layers of Josephson junctions integrated into one process, both for the conventional and {\pi}-junctions., Comment: 8 pages, 7 figures, 1 table, 30 references. Presented at Applied Superconductivity Conference, ASC 2018, Oct. 28 - Nov. 2, 2018, Seattle, WA, USA. Paper 4EOr3B-02

Recent progress in superconductor electronics fabrication has enabled single-flux-quantum (SFQ) digital circuits with close to one million Josephson junctions (JJs) on 1-cm$^2$ chips. Increasing the integration scale further is challenging because of the large area of SFQ logic cells, mainly determined by the area of resistively shunted Nb/AlO$_x$-Al/Nb JJs and geometrical inductors utilizing multiple layers of Nb. To overcome these challenges, we are developing a fabrication process with self-shunted high-J$_c$ JJs and compact thin-film MoN$_x$ kinetic inductors instead of geometrical inductors. We present fabrication details and properties of MoN$_x$ films with a wide range of T$_c$, including residual stress, electrical resistivity, critical current, and magnetic field penetration depth {\lambda}$_0$. As kinetic inductors, we implemented Mo$_2$N films with T$_c$ about 8 K, {\lambda}$_0$ about 0.51 {\mu}m, and inductance adjustable in the range from 2 to 8 pH/sq. We also present data on fabrication and electrical characterization of Nb-based self-shunted JJs with AlO$_x$ tunnel barriers and J$_c$ = 0.6 mA/{\mu}m$^2$, and with 10-nm thick Si$_{1-x}$Nb$_x$ barriers, with x from 0.03 to 0.15, fabricated on 200-mm wafers by co-sputtering. We demonstrate that the electron transport mechanism in Si$_{1-x}$Nb$_x$ barriers at x < 0.08 is inelastic resonant tunneling via chains of multiple localized states. At larger x, their Josephson characteristics are strongly dependent on x and residual stress in Nb electrodes, and in general are inferior to AlO$_x$ tunnel barriers., Comment: 12 pages, 14 figures, 1 table, 51 references. Presented at the 13th European Conference on Applied Superconductivity, EUCAS 2017, 17-21 September 2017, Geneva, Switzerland

Existing concepts of reversible superconducting circuits as well as demonstrated adiabatic circuits require three-phase bias/clock signals generated by room temperature sources. A while ago, we suggested that a multi-phase bias/clock could be provided by a local Josephson junction-based generator. The generator looks like a long annular Josephson junction, only composed of discreet elements - junctions and inductors, and closed into a ring via a flux pump to inject any required number of vortices into the ring. A steady motion of the vortices forced by a uniformly distributed dc bias current applied to the ring is accompanied by a nearly harmonic ac currents flowing via the Josephson junctions (JJs) connected in series with small inductors. These ac currents serve as multi-phase bias/clock for nSQUID-based circuitry. To verify this concept and compare the dissipated energy with kBTln2 threshold, we developed a ring composed of 256 unshunted JJs with 20 {\mu}A target critical current, Ic. We investigated the behavior of the ring oscillator at each vortex count from 0 to 256. The measured critical current of the ring with vortices was about 0.1 {\mu}A per one JJ, which can be explained by unavoidable nonuniformity of the ring components and the influence of fluxes frozen near the ring. The corresponding energy dissipation, about 10kBT per passage of one vortex through one JJ, should be reduced further for prospective experiments with reversible circuits. However, obtained I-V characteristics could be of interest for scientists working with long Josephson junctions. Superiority of the fabrication process used in this work is demonstrated by the obtained about 200 times reduction of Ic of the ring with vortices with respect to a single comprising JJ, much larger than in any previously described case., Comment: Extended Abstract: 3 pages, 3 figures, 10 references. Submitted for presentation at the 16th International Superconductive Electronics Conference, ISEC 2017, 12-16 June 2017, Sorrento, Italy

We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 {\mu}m made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity., Comment: Extended Abstract: 3 pages, 4 figures, 1 Table, 9 references. 16th International Superconductive Electronics Conference, ISEC 2017, 12-16 June 2017, Sorrento, Italy

We develop an ac-biased shift register introduced in our previous work (V.K. Semenov et al., IEEE Trans. Appl. Supercond., vol. 25, no. 3, 1301507, June 2015) into a benchmark circuit for evaluation of superconductor electronics fabrication technology. The developed testing technique allows for extracting margins of all individual cells in the shift register, which in turn makes it possible to estimate statistical distribution of Josephson junctions in the circuit. We applied this approach to successfully test registers having 8, 16, 36, and 202 thousand cells and, respectively, about 33000, 65000, 144000, and 809000 Josephson junctions. The circuits were fabricated at MIT Lincoln Laboratory, using a fully planarized process, 0.4 {\mu}m inductor linewidth, and 1.33x10^6 cm^-2 junction density. They are presently the largest operational superconducting SFQ circuits ever made. The developed technique distinguishes between hard defects (fabrication-related) and soft defects (measurement-related) and locates them in the circuit. The soft defects are specific to superconducting circuits and caused by magnetic flux trapping either inside the active cells or in the dedicated flux-trapping moats near the cells. The number and distribution of soft defects depend on the ambient magnetic field and vary with thermal cycling even if done in the same magnetic environment., Comment: 8 pages, 12 figures, 1 table, 15 references This work was presented at Applied Superconductivity Conference, ASC2016, Denver CO, September 4-9, 2016. Submitted to IEEE Transactions on Applied Superconductivity on 6 September 2016

We investigated current-voltage characteristics of unshunted and externally shunted Josephson junctions (JJs) with high critical current densities, Jc, in order to extract their basic parameters and statistical characteristics for JJ modeling in superconducting integrated circuits and to assess their potential for future technology nodes. Nb/AlOx-Al/Nb JJs with diameters from 0.5 {\mu}m to 6 {\mu}m were fabricated using a fully planarized process with Mo or MoNx thin-film shunt resistors with sheet resistance Rsq = 2 {\Omega}/sq and Rsq = 6 {\Omega}/sq, respectively. We used our standard MIT LL process SFQ5ee to fabricate JJs with Jc = 0.1 mA/{\mu}m^2 and our new process SFQ5hs to make JJs with Jc = 0.2 mA/{\mu}m^2 and higher current densities up to about 1 mA/{\mu}m^2. Using LRC resonance features on the I-V characteristics of shunted JJs, we extract the inductance associated with molybdenum shunt resistors of 1.4 pH/sq. The main part this inductance, about 1.1 pH/sq, is the inductance of the 40-nm Mo resistor film, while the geometrical inductance of superconducting Nb wiring contributes the rest. We attribute this large inductance to kinetic inductance arising from the complex conductivity of a thin normal-metal film in an electromagnetic field with angular frequency {\omega}, {\sigma}({\omega})={\sigma}0/(1+i{\omega}{\tau}), where {\sigma}0 is the static conductivity and {\tau} the electron scattering time. Using a resonance in a large-area unshunted high-Jc junction excited by a resistively coupled small-area shunted JJ, we extract the Josephson plasma frequency and specific capacitance of high-Jc junctions in 0.1 to 1 mA/{\mu}m^2 Jc range. We also present data on Jc targeting and JJ critical current spreads. We discuss using 0.2-mA/{\mu}m^2 JJs in VLSI Single Flux Quantum circuits and 0.5-mA/{\mu}m^2 JJs in high-density integrated circuits without shunt resistors., Comment: 15 pages, 22 figures, 2 tables, 52 references. Presented at Applied Superconductivity Conference, ASC 2016, Denver CO, September 4-9, 2016. Submitted to IEEE Transaction on Applied Superconductivity on September 2, 2016

Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin superconducting layer for making compact high-kinetic-inductance bias inductors. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The physical limitations imposed on the circuit density by Josephson junctions, circuit inductors, shunt and bias resistors, etc., are discussed. Energy dissipation in superconducting circuits is also reviewed in order to estimate whether this technology, which requires cryogenic refrigeration, can be energy efficient. Fabrication process development required for increasing the density of superconductor digital circuits by a factor of ten and achieving densities above 10^7 Josephson junctions per cm^2 is described., Comment: 20 pages, 14 figures, 153 references, submitted to Low Temperature Physics

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ) digital circuits with very large scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where 'ee' denotes the process is tuned for energy efficient SFQ circuits. The former has eight superconducting layers with 0.5 {\mu}m minimum feature size and a 2 {\Omega}/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc < 2 K) MoNx layer with lower nitrogen content is used for 6 {\Omega}/sq planar resistors for shunting and biasing of Josephson junctions. Another resistive layer is added to form interlayer, sandwich-type resistors of m{\Omega} range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density, Jc of 100 {\mu}A/{\mu}m^2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, critical current and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high kinetic inductance layer, technology of m{\Omega}-range resistors., Comment: 10 pages, 12 figures, 1 table, 27 references. The paper was presented on September 8, 2015 at the 12th European Conference on Applied Superconductivity, EUCAS 2015, 6-10 September 2015, Lyon, France, IEEE Transaction on Applied Superconductivity, 2016

Recent progress of Reciprocal Quantum Logic (RQL) has renewed interest in AC powering of superconductor digital circuits, which had been abandoned since the famous IBM project of 1970s. In this work we propose and demonstrate new AC-biased Single Flux Quantum (SFQ) circuits, and search for synergy of AC and currently dominating DC biasing schemes. As the first step, we suggest an on-chip AC/DC converter capable of feeding a few DC-biased gates surrounded by their AC-biased counterparts. As the second step, we introduce and present the first successful demonstration of a new AC-powered circuit - an 8192-bit shift register with over 32,800 Josephson junctions (JJs) and JJ density of about 6x$10^5$ JJ per $cm^2$. We suggest a few niche applications for this type of AC-biased circuits, not requiring high clock rates. E.g., these, scalable to millions of JJs per chip, circuits can serve as a convenient benchmark for new SFQ fabrication technology nodes, allowing the operating margins of individual cells to be extracted and, thus, 'visualize' individual fabrication defects and flux trapping events. The circuit can also be developed into a mega-pixel imaging array for a magnetic field microscope., Comment: 7 pages, 10 figures, 33 references. Presented at Applied superconductivity Conference ASC 2014, August 10-15, 2014, Charlotte, NC, USA

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90-degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities > 10^6 Josephson junctions per cm^2 are discussed., Comment: 5 pages, 7 figures, 31 references. Presented at Applied Superconductivity Conference, ASC 2014, Charlotte, NC, USA, August 10-15, 2014

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO$_2$ interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, $I_c$, normal-state conductance, $G_N$, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, $J_c$, from 10 kA/$cm^2$ to 50 kA/$cm^2$ where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The $G_N$ and $I_c$ spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. $I_c$ and $G_N$ spreads from 0.8% to 3% have been obtained for JJs with sizes from 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > $10^6$ JJ/$cm^2$ and 193-nm photolithography for JJ definition are discussed., Comment: 13 pages, 16 figures, 62 references. Presented at Applied Superconductivity Conference, ASC 2014, Charlotte, NC, USA, August 10-15, 2014

A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented in the normal and superconducting states. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/{\mu}m2 and approaches the depairing current density of Nb films., Comment: 13 pages, 11 figures, 24 references. Presented on September 16, 2013 at the 11th European Conference on Applied Superconductivity EUCAS 2013, 15-19 September 2013, Genoa, Italy

New technology for superconductor integrated circuits has been developed and is presented. It employs diffusion stoplayers (DSLs) to protect Josephson junctions (JJs) from interlayer migration of impurities, improve JJ critical current (Ic) targeting and reproducibility, eliminate aging, and eliminate pattern-dependent effects in Ic and tunneling characteristics of Nb/Al/AlOx/Nb junctions in integrated circuits. The latter effects were recently found in Nb-based JJs integrated into multilayered digital circuits. E.g., it was found that Josephson critical current density (Jc) may depend on the JJ's environment, on the type and size of metal layers making contact to niobium base (BE) and counter electrodes (CE) of the junction, and also change with time. Such Jc variations within a circuit reduce circuit performance and yield, and restrict integration scale. This variability of JJs is explained as caused by hydrogen contamination of Nb layers during wafer processing, which changes the height and structural properties of AlOx tunnel barrier. Redistribution of hydrogen impurities between JJ electrodes and other circuit layers by diffusion along Nb wires and through contacts between layers causes long-term drift of Jc. At least two DSLs are required to completely protect JJs from impurity diffusion effects - right below the junction BE and right above the junction CE. The simplest and the most technologically convenient DSLs we have found are thin (from 3 nm to 10 nm) layers of Al. They were deposited in-situ under the BE layer, thus forming an Al/Nb/Al/AlOx/Nb penta-layer, and under the first wiring layer to junctions' CE, thus forming an Al/Nb wiring bi-layer. A significant improvement of Jc uniformity on 150-mm wafer has also been obtained along with large improvements in Jc targeting and run-to-run reproducibility., Comment: 7 pages, 9 figures; to be published in IEEE Transactions of Applied Superconductivity

Currently, superconductor digital integrated circuits fabricated at HYPRES, Inc. can operate at clock frequencies of ~ 40 GHz. The circuits present multilayered structures containing tens of thousands of Nb/Al/AlOx/Nb Josephson junctions (JJs) of various sizes interconnected by four Nb wiring layers, resistors, and other circuit elements. In order to be operational, the integrated circuits should be fabricated such that the critical currents of Josephson junctions remain within the tight design margins and the proper relationships between the critical currents of JJs of different sizes are preserved. We present experimental data and discuss mechanisms of process-induced variations of the critical current and energy gap of Nb/Al/AlOx/Nb Josephson junctions in integrated circuits. We demonstrate that the Josephson critical current may depend on the type and area of circuit elements connected to the junction, on the circuit pattern, and on the step in the fabrication process at which the connection is made. In particular, we discuss the influence of a) junction base electrode connection to ground plane, b) junction counter electrode connection to ground plane, and c) counter electrode connection to Ti/Au or Ti/Pd/Au contact pads by Nb wiring. We show that the process-induced changes of the properties of Nb/Al/AlOx/Nb junctions are caused by migration of impurity atoms (hydrogen) between different layers comprising the integrated circuits.

The effect of dc electrical stress and breakdown on Josephson and quasiparticle tunneling in Nb/Al/AlOx/Nb junctions with ultrathin AlOx barriers typical for applications in superconductor digital electronics has been investigated. The junctions' conductance at room temperature and current-voltage (I-V) characteristics at 4.2 K have been measured after the consecutive stressing of the tunnel barrier at room temperature. Electrical stress was applied using current ramps with increasing amplitude ranging from 0 to ~1000 Ic corresponding to voltages across the barrier up to 0.65 V where Ic is the Josephson critical current. A very soft breakdown has been observed with polarity-dependent breakdown current (voltage). A dramatic increase in subgap conductance of the junctions, the appearance of subharmonic current steps, and gradual increase in both the critical and the excess currents as well as a decrease in the normal-state resistance have been observed. The observed changes in superconducting tunneling suggest a model in which a progressively increasing number of defects and associated additional conduction channels (superconducting quantum point contacts (SQPCs)) are induced by electric field in the tunnel barrier. By comparing the I-V characteristics of these conduction channels with the nonstationary theory of current transport in SQPCs based on multiple Andreev reflections by Averin and Bardas, the typical transparency D of the induced SQPCs was estimated as D ~ 0.7. The number of induced SQPCs was found to grow with voltage across the barrier as sinh(V/V_0) with V_0 = 0.045 V, in good agreement with the proposed model of defect formation by ion electromigration. The observed polarity dependence of the breakdown current (voltage) is also consistent with the model., Comment: 11 pages, 10 figures