Search

This paper presents a highly efficient dual-mode HV (high voltage) buck converter which operates at both light and heavy load currents. To improve the conversion efficiency at two different load conditions, a dual-mode design composed of pulse width modulation (PWM) and pulse frequency modulation (PFM) were implemented using TSMC 0.5- $\mu $ μ m HV CMOS process. The chip area is 2038.05 $ \times $ × 1689.85 $\mu $ μ m2, while the input voltage ranges from 12 V to 15 V. A 92.95% peak efficiency at a load current of 10 mA was achieved based on on-silicon measurement results. [ABSTRACT FROM AUTHOR]

The resolution of time-to-digital converters (TDC) is one parameter that will define its efficiency. This research demonstrates a 5.4 ps TDC with anti-PVT-variation implemented in 90-nm CMOS technology. The proposed converter uses a two-step architecture. The first stage is a Buffer Delay Line (BDL) to acquire a wide dynamic range characteristic. The second stage that will provide a higher resolution is Vernier delay line which receives the start and stop signals from the edge detector. A PVT (process, voltage, temperature) corner detector is equipped in the proposed TDC to resist the PVT variation. The proposed TDC's post-layout simulation results achieve a delay variation of 2 ps and a resolution of 5.4 ps, and an acceptable dynamic range of 890 ps. The INL and DNL attained a value of 0.8 and −1 LSB from the simulations. The proposed TDC attains the best FOM based on post-layout simulations with a value of 0.177, which makes it superior to all prior designs. [ABSTRACT FROM AUTHOR]

Underwater images often encounter challenges such as attenuation, color distortion, and noise caused by artificial lighting sources. These imperfections not only degrade image quality but also impose constraints on related application tasks. Improving underwater image quality is crucial for underwater activities. However, obtaining clear underwater images has been a challenge, because scattering and blur hinder the rendering of true underwater colors, affecting the accuracy of underwater exploration. Therefore, this paper proposes a new deep network model for single underwater image enhancement. More specifically, our framework includes a light field module (LFM) and sketch module, aiming at the generation of a light field map of the target image for improving the color representation and preserving the details of the original image by providing contour information. The restored underwater image is gradually enhanced, guided by the light field map. The experimental results show the better image restoration effectiveness, both quantitatively and qualitatively, of the proposed method with a lower (or comparable) computing cost, compared with the state-of-the-art approaches. [ABSTRACT FROM AUTHOR]

This investigation demonstrates a 10-bit SAR-ADC with low power dissipation per conversion step at 50 MS/s sampling rate. The proposed ADC is featured with the split-capacitance array by using unity-gain amplifiers and designed for fibre optic gyroscope (FOG) systems. The buffers based on the unity-gain amplifiers replace the bridge capacitors of the split-capacitance array in conventional SAR ADCs to resist process variation and enhance linearity of the capacitor-array. Aside from those, improvements in time response, that is, settling time, and capacitor size have also been proved. The design was implemented using a typical 40-nm CMOS process. The INL (integral non-linearity) and the DNL (differential non-linearity) were found to be 0.56 LSB and 0.51 LSB, respectively. The SNDR and SFDR are 51.23 dB and 61.46 dB, respectively, at an input of 12.5 MHz showing ENOB to be 9.79 bits at a sampling rate of 50 MS/s. [ABSTRACT FROM AUTHOR]

By keeping the very same transmission rate, a scheme is provided by DETFF (double-edge triggered flip-flops) for power dissipation reduction. As a result, they are suitable for use as shift registers. This investigation discussed various previous DETFF designs and demonstrated a new DETFF circuit applied to construct an 8-bit low-power shift register. This study makes a significant contribution by using two parallel data paths that operate in a single clock's opposing phases where an inverted input trigger is unnecessary. TSMC 90-nm complementary metal-oxide semiconductor (CMOS) technology was used to implement the proposed shift register. Comparing the proposed DETFF with prior works, it has fewer transistor counts since the negated input trigger and auxiliary devices were removed, resulting in lower area cost and lower power dissipation. At 100 MHz clock frequency and lower supply voltage of 1.0 V, it demonstrates a power consumption of 3.352 mW on silicon, making it suitable for low-power applications. Lastly, it has the best performance compared with prior works speaking of larger scale, as demonstrated by the chip's functionality and jitter measurement at the maximum frequency of 200 MHz. [ABSTRACT FROM AUTHOR]

This research illustrates a DC–DC buck converter with a pulse width modulation (PWM) feedback control loop and capable of power supply voltage range from VDD to 2.5× VDD, which is equivalent to 5–14 V. It is a single chip with area of 1.379 × 0.813 mm2 using 0.5 µm HV CMOS process, where high voltage (HV) MOSFETs, a Dead-time detector, a PWM feedback loop, a control circuit and HV driving transistors are included. The main feature of our design is its capability of shutting off an optimal number of power MOSFETs during light load operation, resulting in a very high conversion efficiency. Most important of all, the optimal solution is analytically proved. The light load efficiency is raised from 31.71% by traditional methods to 67.94% by the proposed design. [ABSTRACT FROM AUTHOR]