32 results on '"Yoo, Taegeun"'
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2. A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices
3. Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks
4. A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks
5. A Low-Power Smart Gesture Sensing SoC with On-chip Image Sensor for Smart Devices
6. Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks
7. Pressure effects on high temperature steam oxidation of zircaloy-4
8. A 137-μW 1.78-mm2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices
9. A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines
10. SRAM Radiation Hardening Through Self-Refresh Operation and Error Correction
11. A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length
12. A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC
13. A 0.5 V 8–12 Bit 300 KSPS SAR ADC With Adaptive Conversion Time Detection-and-Control for High Immunity to PVT Variations
14. A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks
15. A 213.7-$\mu$ W Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm
16. A 213.7-µW Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm
17. A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation
18. An 88% efficiency 0.1–300-μW energy harvesting system with 3-D MPPT using switch width modulation for IoT smart nodes
19. A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks
20. A 12-bit Multi-Channel R-R DAC Using a Shared Resistor String Scheme for Area-Efficient Display Source Driver
21. An Ultra-low Power 8T SRAM with Vertical Read Word Line and Data Aware Write Assist
22. A 0.016 mV/mA Cross-Regulation 5-Output SIMO DC–DC Buck Converter Using Output-Voltage-Aware Charge Control Scheme
23. A Radiation Hardened SRAM with Self-refresh and Compact Error Correction
24. A 137-μW Area-Efficient Real-Time Gesture Recognition System for Smart Wearable Devices
25. An 88% Efficiency 0.1–300- $\mu$W Energy Harvesting System With 3-D MPPT Using Switch Width Modulation for IoT Smart Nodes
26. A return-to-zero DAC with tri-state switching scheme for multiple nyquist operations
27. Energy-efficient Spread Second Capacitor Capacitive DAC for SAR ADC
28. An 88% efficiency MPPT for PV energy harvesting system with novel switch width modulation for output power 100nW to 0.3mW
29. An 88% Efficiency 0.1–300- $\mu$ W Energy Harvesting System With 3-D MPPT Using Switch Width Modulation for IoT Smart Nodes.
30. Efficient Maximum Power Point Tracking for a Distributed PV System under Rapidly Changing Environmental Conditions
31. A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS
32. 21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS
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