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This paper will discuss a topological layout project for IC components using a computer, based on given circuit diagrams and order of bonding pads.

This paper concerns switching networks which consist of n identical combinational logic cells interconnected from left to right by alpha communication channels into linear arrays. The synchronous cells in these networks have unit switching delays separating their receipts of external x and left-neighbor alpha inputs from their corresponding productions of external z and right-neighbor alpha outputs. Three basic types of alpha transient behavior are discussed for such networks. In the first type, all transients extend to no more than a bounded number of cells to the right of each x change; in the second, all transients propagate all the way to the right boundary of the network; and in the third, any transient may or may not propagate to the right boundary of the network depending upon the x sequence to the right of the x change in question. In all three cases, necessary and sufficient conditions are given on the type of alpha logic allowed. These conditions are expressed in terms of corresponding alpha state graph structure. The paper's main results hinge on certain properties of a new type of state subgraph, and on an indirect application of permutation groups to the state-pair transition problem. A section of examples proves that individual graphs can contain any mixture of the above three types of transient behavior.

This paper presents an extension of the Muller-Bartky theory of asynchronous switching circuits. A circuit specification is a set of vectors whose components are non-negative integers and which satisfies certain other conditions. The j-th component of such a vector represents the number of times which the signal at the j-th node has changed since the circuit was started. The principal result of the paper characterizes the class of circuit specifications which may be realized by semimodular switching circuits. An alternative method of circuit specification is defined and shown to be equivalent.

Previous papers have shown that for any given n-input synchronous sequential machine there exists a circuit realization in which the circuit consists of a finite number of identical copies of one module and in which the modules are interconnected in a uniform manner. This paper shows that additionally the signal fan-in to every module and the signal fan-out from every module and from the input can be bounded by a constant and that the modules can be interconnected in a planar structure. This paper also investigates several properties of these circuits and establishes several necessary conditions that these circuits must have. Two desirable design goals are shown to be simultaneously unachievable

In this paper a frequency-domain adaptive array structure is derived that processes data in selected regions of frequency-wave-number space to provide an MMSE estimate of a signal component of the observed acoustic field. The desired "optimal" processor structure is derived by appealing to the Sherman-Morrison inversion lemma to invert the sum of a diagonal noise matrix and several diadic matrices corresponding to plane-wave propagating signal and interference fields. The structure reduces to a parallel structure of beamformer-gain elements whose beamformer directions (phase delays) and gains are unknown because of a priori ignorance concerning interference directions and levels. The structure is adapted to these uncertainties by forming a stochastic approximation algorithm for the gains of several beams directed to a finite set of possible interference directions.

A frequency-transformation is introduced which maps a low-pass ladder network into a ladder of transmission-lines of prescribed length. A non-redundant coupled-line realization is given for proto-types having transmission-zeros either at finite or at infinite frequencies. The design method is both theoretically and practically suitable for the design of narrow and broad band filters. In the paper theory, design steps as well as computational and measuring results are given.

A computer-aided topological layout of components and wiring in integrated circuits will presented based on a new kind of graph which accounts for all technological restrictions, as well as possibilities.

It can he easily shown that any combinational circuit with only uncomplemented inputs can be realized using three stages of NOR logic. However, if such a circuit is designed by a direct extension of the theory of two-stage circuits using AND Gates and OR Gates. the result- will not be an efficient circuit. In order to design such NOR gate circuits efficiently it is necessary to modify the design techniques so that the third stage gates (those driven directly by the inputs) are. chosen properly. In partioular, it is necessary to allow for the possibility that a gate realizing. a function such as a1 + b1 be used in realizing the function ab1 + a1b as a(a1+b1) + b(a1+b1) rather than two separate gates to generate a1 and b1. A general technique for the design of such circuits is presented in this paper. Interesting features in the design of such networks arise from the fact. that their cost is effected by complementing some of the variables in the functlon.

This paper presents a simplified solution of complex coupling problems in both the frequency and time domain, that are common in the Aerospace industry. This approach consists in determining the transfer function (coupling factor), that exists between the interference and induced lines, using modified Electromagnetic Directional Coupler equations. Graphical techniques are presented to facilitate rapid solutions.

This paper introduces the concept of a controllability module and then uses it to study certain algebraic properties of index-invariant, time-varying, linear systems. It is shown that controllability modules possess a property similar to the pole placement property of controllability subspaces. Application of controllability modules to index-invariant systems leads to a new construction of Brunovský’s decomposition which serves to clarify the algebraic relationships upon which the decomposition is based.

In designing varactor multiplier chains, it is normally necessary to include isolators between the multipliers in order to eliminate spurious signals which are due to parametric oscillations. These oscillations can occur when two adjacent multipliers are not perfectly matched. In this paper, we shall present a method for the design of multiplier chains which are highly stable, eliminating the need for isolators.

This paper develops expressions for the spectral power density of a simple triode amplifier. The technique employed is straight-forward and employs a nonlinear triode model based on a piecewise linear approximation to the static characteristics of the device. The technique is not restricted to triodes and may, employing the proper device model, be used to solve other types of amplifiers. The solution is given as an iterative process of successive approximations.

Cascade switching circuits include collapsed-tree, iterative, sequential, multiple iterative, and cascaded sequential switching circuits. The cost of such a circuit is dependent on the order in which the input variables are applied to the circuit. This paper reviews a previously described procedure for the synthesis of cascade circuits and shows how it may be adapted so as to non-enumeratively determine the ordering of the variables which results in the lowest cost circuit.

This paper presents a synthesis method to realize any p-state normal asynchronous sequential circuit A according to an unconventional structure. It consists of two critical-race free S.T.T. normal asynchronous circuits A1 and A2 connected in series, where A1 is realized with L internal variables and A2 with 2 ? So internal variables (So = [ log2 p] ). It is shown that L = 1 for circuit A with single inpunt transitions, and that L is equal to the number of input terminals of A for circuit with multiple input transitions. The internal structure of circuit A2 is investigated by using partition algebra. As a result of this investigation it is shown that A2 can always be realized according to a general model with only So feedback paths, each one including a master-slave flip-flop. Using this model and a straigtforward synthesis procedure, any p-state normal asynchronous circuit can therefore be realized by So + L feed-back Paths.

The increased use of microstrip transmission line for miniaturized printed microwave circuits has created a demand for a compact filter structure compatible with microstrip. The parallel coupled filter circuits developed by Cohn are very compact, but his design procedure does not apply to microstrip which has different even and odd mode velocities. This paper develops the theoretical analysis to compensate Cohn's procedure for even and odd mode velocity differences and develops design curves which permit the determination of the circuit geometry from the parameter K/Z/sub o/. The results only apply to filters with 50 /spl Omega/ impedance on 99.5% alumina substrates, but they can easily be generalized to other impedances.

This paper presents the development of the time behavior of an arbitrary n-element adaptive array using finite dimensional spectral theory, whose performance measure is the minimum mean square criterion. In particular, an environment consisting of a target or desired emitter and one interference source is focused on and the weight trajectory, signal -to-noise power ratio and gain are evaluated.

This paper describes a procedure for synthesizing transmission networks which are interconnections of uniform line elements. An iterative, digital computer algorithm is developed which achieves a dominant pole synthesis. The line lengths and the characteristic impedances are controlled individually, which gives design flexibility not found in synthesis procedures based on Richard's transformation. Thus, the characteristic impedances may be restricted by upper and lower bounds when there is no restriction on the line lengths. The procedure is detailed for a TEM mode structure of alternating open stubs and connecting lines. The method uses a Newton-Raphson iterative scheme to adjust the characteristic impedances and lengths of the transmission lines for a prescribed set of dominant transmission poles. If the poles are chosen to give a low-pass characteristic when all of the transmission zeros are at infinity, the finite transmission zeros produced by the stubs modify substantially the transfer characteristic realised. By controlling the stub line lengths and modifying the dominant pole positions an improved transmission characteristic and bounded characteristic impedances can be achieved simultaneously.

One of the earliest-developed and still widely-used dc to square-wave inverters is the Royeror Uchrin-Taylor configuration shown in Fig. 1. Although the circuit is composed of very few components, its proper operation depends on complex interactions of the transformer as it switches between its unsaturated and saturated regions, and the tow transistors as they switch between cut-off and saturation. Numerous qualitative descriptions of the operation of this circuit have been presented; however, the complexities introduced by the multiple nonlinearities are such that few mathematically based analyses have been presented, and these have been rather limited in scope (1,2,3,4). The analysis presented in this paper provides insight not only into steady-state operation but also into the transient behavior of the circuit. It also makes evident the influence of certain small, often neglected, parasitic elements such as winding capacitance, transformer saturation inductance, and semiconductor junction capacitances.