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A novel high-performance processor architecture for processing a large number of independent instruction streams is proposed and its operating behavior studied. The proposed processor operates on instruction words in a two-address format (thereby eliminating the "operating registers"), and is organized in a fashion which permits as high degree of internal buffering and pipelining. The processor has the following properties: 1) The hardware cost grows only slightly more than linearly with the overall implementation cost; 2) The overall performance is primarily dependent on the processor wordtime and is only secondarily dependent on the supporting memory cycle time; 3) All instruction stream interfaces with memory occur at special queuing (buffer) units which are used to "unscramble" the instruction streams and continually provide work for subsequent processing elements.

A number of significant architectural concepts which have evolved in recent years are reviewed. These concepts are: the notion of process and the facilities for process management, such as dispatching and synchronization; the use of segmentation in organizing address spaces, and the resulting sharing and protection capabilities; the control of access to data and procedures via multiple privilege levels; the use of automatic stack management for procedure calling; and the structure of logical and physical I/O channels and I/O operations queueing. The rationale for including these concepts in modem central processor architectures, such as in the Honeywell Series 60, is also presented.

To overcome many difficulties besetting the design of a cost-effective stored-program telephone switch control, this paper proposes a systematic three-step approach: 1) selection from twelve basic subclasses of a software organization satisfying flexibility, reliability, and speed-of-service constraints; 2) estimation of program size and processing load assuming a rudimentary processor architecture; and 3) determination of an optimal stored-program-wired-logic boundary and a minimum cost processor architecture. The last step is simplified by using a quantitative criterion called speed-size ratio.

International audience; The microarchitecture of the MC68000 microprocessor is examined, including technological and system characteristics, resources, instructions, signals exceptions and test mode. The internal architecture is detailed: data processing section and control section. Next basic rules for the design of self-checking NMOS circuits are briefly given. These rules are based on fault hypotheses including for example transistors s-open/s-on, shorts between aluminum lines, etc. The application of these rules to the design of a self-checking version of the MC68000 is not detailed, but an evaluation of what should be such a redesign is given. The silicon overhead is detailed.