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The patent relates to an improvement in a counter system wherein the count is available immediately after the reception of the counting clock pulse. Thus, there is no need to wait for a successive ripple-through, and the possibility of erroneous outputs due to an intermediate ripple-through state is eliminated. The circuitry employed to accomplish the invention includes among other things, a ripple-through binary counter coupled to an n-bit parrallel register.

This report describes the results of Phase I of the Gallium Arsenide Digital Integrated Circuits program, which was intended to demonstrate the feasibility of fabricating digital circuits with GaAs metal-semiconductor field-effect transistor (MESFET) technology. Dc, RF and switching parameters of the GaAs MESFET were characterized, a large-signal nonlinear device model developed and verified with the characterization data and a MESFET logic gate fabricated. The logic gate exhibited a propagation delay of 60 ps plus 15 ps per output load and a useful bandwidth of 3-4 GHz. Based on these experimental results, it is predicted that practical medium-scale logic systems with 2-3 GHz clock rates will be possible. Progress in the development of a MESFET process with self-aligned gate is reported. (Author)

The report describes in detail the circuitry of a multirange-gate pulse doppler radar which operates at 400 MHz. The system is a low power one that generates only a one-watt (peak) pulse of 50 ns length at a 40 kHz rate, for an average power of 2 mW. The receiver employs RF amplification, a wide-band video amplifier following the coherent mixer, a set of boxcars used as range gates, and active high-pass filters which are voltage adjustable. The timing circuit required is discussed.

Edited trans. of mono. Mnogoustoichivye Elementii i Ikh Primenenie. Sbornik Statei, n.p., 1971 p162-169, by Frank C. Vaughn.

Edited trans. of mono. Mnogoustoichivye Elementy i ikh Primenenie. Sbornik Statei, n.p., 1971 p202-206, by James R. Moore.

Edited trans. of mono. Mnogoustoichivye Elementy i ikh Primenenie. Sbornik Statei, n.p., 1971 p119-123, by Charles T. Ostertag, Jr.

The detailed logical design is given for a serial digital computer using a 0.5-microsecond magnetic memory, 100-mc logical circuits, and one-word delay lines. The computer performs most instructions in 1 microsecond. A list is given of the amount of hardware used.

The Programmable Film Reader, consisting of digital computer, magnetic tape units, CRT, and film transport with optical and electronic circuits, is a device for reducing radar A-scope film data to digital form. This is done by scanning selected portions of the film with a spot of light under program control. The relative amount of light passing through the film is measured by the device and reported back to the computer for processing. A set of computer programs, called the Film Reading Program System, has been written for the PDP-1 computer and Programmable Film Reader. These programs will read films in three formats; A-scope traces, A-scope traces with fiducial marks and Project Radar A-scope traces. The amplitudes of the traces are sampled up to about 500 times and the digitized results written onto magnetic tape in IBM format. This report presents a description of the computer programs together with flow charts and listings. The reader is presumed familiar with the PDP-1 computer and the MACRO assembly language. The latest modification to the system adapts it for use with the MIDAS assembly program and with a new high-speed magnetic tape system on the PDP-1 computer., Available copy will not permit fully legible reproduction.

It is very important for the operation of the Lincoln Data Recovery Center to be able to inject into it artificially generated targets. These target-pulses must simulate as closely as possible those appearing in the input from the I. F. tape into the D. R. C. and should be controllable in range, width, amplitude, phase and repetition rate by special computer programs written for the CDC-3200 computer. In addition to the FM channels of the tape, its digital channels must be simulated. A target simulator was constructed to the above specifications and is described.

The effects of nuclear radiation on the telemetry circuits in the LES satellites have been analysed by direct irradiation and by simulating the effects on individual components on a breadboarded circuit. The simulation method is described in detail. It requires a precise knowledge of the behavior of each component operating under specified bias conditions in a radiation environment, but may be applied to circuits of considerable complexity. The analysis confirmed that circuits such as the flip-flop, which operate at 50 per cent duty cycle, are insensitive to moderate leakage currents and have low gain requirements, are extremely radiation resistant. The converse holds for circuits that operate at low duty cycles, that are sensitive to leakage currents and that have more stringent gain requirements.

This engineering research program, undertaken to construct a 5000 word cryogenic associative data processor, achieved its intermediate objectives concerning identification and solution of technical limitations for large capacity array fabrication, interconnection, data linkage, and packaging. Successful methods for fabricating 2.0 inch x 2.25 inch arrays having 40-word, 2000-cell (11,000 cryotrons) capacities resulted in seven operable arrays by the end of the program. Between 126 and 144 such arrays would provide the 5000 word objective. Fault-tolerant system operation permits use of arrays containing failed word(s). Array interconnection via superconducting, flexible, strip transmission line in pressure-actuated contact with thin film array contacts was successfully used throughout the contract, as were preferred data linkage means. Design concepts for packaging the multi-array system were accomplished, and the interface electronic functions to permit on-line operation with a Univac 1218(M) computer were specified. Because solution of array fabrication problems consumed most of the contract period, fabrication of the full complement of arrays was not possible. An engineering development program is recommended for construction of the 5000 word cryogenic associative processor.

Progress in the design and development of a family of regulated filament supplies utilizing semiconductor electronics throughout is reported. A model 20 ampere supply was constructed representative of electrical and mechanical techniques to be used for the family of filament supplies. Preliminary tests show that the model supply meets the specified electrical requirements. Initial measurements on the model 6.3 v, 20 amp filament supply based on the nondissipative technique show that the true rms output voltage exhibits an almost undetectable variation over the entire line-load continum of 103 to 127v line variation and no load to 20 amp load variation. The full load efficiency was greater than 90%. The major remaining problem is the suppression of radio frequency interference. The work to date in the high voltage supplies consists of the breadboarding of a 4kv dc regulated supply based on the Royer Transistor square wave inverter circuit. This circuit will provide an output voltage continuously variable between 2 and 4kv. With the use of voltage doublers and quadruplers the entire high voltage range of 4 to 16kv can be supplied. (Author)

Describes the implementation of the Component Division and Placement Module of a Design Automation System. The module accepts as input the equivalent of a logic diagram with designer specification of a class of possible logic devices to which each logic element on the diagram belongs. One must also specify the physical characteristics of the electronic devices, the number and type of each device, and the packaging system to be used. The devices on the logic diagram are then assigned to the physical hardware available. Additional designer specifications such as 'logical grouping' have been implemented, and the characterization of board assignment has been generalized. (Author)

A device for storing data, consisting of an information analysis unit, synchronizer and a start-stop storage unit, is distinguished by the fact that to reduce the required capacity of the memory and to eliminate loss of information it contains two buffer memories., Edited trans. of Patent (USSR) 226 947 3p, 20 Sep 67, by W. Pearson.

In earlier work, the differential mode (DM) model for sequential networks, in which the state of a sequential machine is given as a function of input and state changes, was introduced and applied to the analysis and synthesis of sequential switching networks. The report further develops the DM model and introduces new synthesis procedures for networks with edge-sensitive flip-flops. (Author)

The report describes research into some properties of autonomous, synchronous counters constructed with only the simplest form of J-K Flip-Flop. The research revolved around a system with a special-purpose digital machine and a general-purpose computer. The special-purpose machine searched through all the possible counters constructed of five or fewer J-K Flip-Flops for all counters with a period equal to that specified by the input to the systems. The descriptions of the counters found were transmitted by the special-purpose machine to the computer. Software analyzed this output data for various attributes, such as counters that cycle the same way independent of their starting-state. Useful information for designers of digital machines, several proofs, and some insight into counters constructed only of J-K Flip-Flops resulted from this analysis., Sponsored in part by DARPA.

A mathematical design for an adaptable IRIG standard commutator based on a ring counter is presented. Operation of a prototype is explained, and complete specifications are included. (Author)

Circuits and constructional details are given of a computer for determining trees of a graph, with up to ten apices. The method of programming of the initial data about the graph, whose trees are required to be determined, is also described. The application of the procedure for finding the trees is illustrated by an example. (Author), Edited machine trans. of Otbor i Peredacha Informatsii (USSR) v69 n21-37 1969, by Edwin P. Pentecost.

In recent years, technological advances have provided the designer of computing hardware with the ability to batch-fabricate large numbers of logic components on a single semiconductor slice. Numerous researchers have investigated the synthesis of various kinds of digital logic by using arrays of identical cells. The dissertation considers cellular arrays whose individual cell functions are determined by parameter flip-flops and logic gates in the cell, rather than by a physical customizing operation during manufacture. Potential advantages of this technique include functional variability after manufacture, more efficient testing, and enhanced failure tolerance. Arrays may be classified according to their generality, i.e., the number and range of the tasks which they are designed to perform. Two significantly different examples of low-generality arrays are presented and analyzed. A new cell schema is introduced which exhibits properties important in the synthesis of high-generality functions. Techniques are presented for improving the match between an array design and the target class of tasks. (Author)

Many digital computers are composed of four dual stationary triggers plus a feedback circuit. In this manner the computing circuit is rather complicated and reading the circuit is a complicated process also. This paper suggests a design of a digital computer from which this complication is eliminated. The operating theory and the direct current design of this computer are given in the paper. (Author), Edited trans. of Tien Tzu Chi Shu (Mainland China) n10 p40-41 1966.

Asynchronous state assignment methods are discussed and certain concepts based on these methods are defined. The discussion includes a review of the two race-free assignment methods developed by Huffman, and a detailed review of the USTT assignment method developed by Tracey. The concepts of transition cube, controlling variable, stationary variable and switching variable are defined. Asynchronous circuits realized with flip-flop or delay memories under USTT and race-free state assignments are examined to determine their vulnerability to critical races, hazards and oscillations under faults. Design rules are developed to make circuits invulnerable to most oscillations. It is shown that the vulnerability of virtually all circuits to critical races under faults cannot be removed without adding redundant state variables. Finally a fault tolerant circuit design is proposed. Using redundancy and a special type of logical realization, the fault behavior of the circuit is constrained such that the set of states which the circuit can take under faults is limited to a small number. A check circuit which will indicate the presence of a fault in the sequential circuit is included. This circuit consists of three gates and can be diagnosed for faults with two tests. (Author)

The use of multistable elements for sequential counting time interval measurement is promising if sampling errors can be reduced. A significant improvement in accuracy can be obtained by using a scale-time conversion of the interval between the start and first digitizing impulse and the interval between the last digitizing impulse and the stop impulse. Thus, no reduction in impulse period and no increase in counter stop requirement is needed., Trans. of mono. Monogoznachnye Elementy i Struktury, n.p., 1967 p174-178.

The complementing flip-flop consisting of primary and auxiliary triggers having separate inputs realized on potential elements, 'AND' elements at the inputs of the primary and auxiliary triggers, and a 'NOT' element coupled to the 'AND' element at the auxiliary trigger inputs is distinguished by the fact that in order to insure functional reliability of the flip-flop under all possible combinations of switching times for potential elements an additional 'NOT' element is inserted into the circuit of the flip-flop; the input of the element is coupled to the output of the 'NOT' element connected to the 'AND' elements of the auxiliary flip-flop while the auxiliary 'NOT' element output is coupled to the 'AND' element inputs at the inputs of the primary flip-flop., Edited trans. of Patent (USSR) 343 385 p1-2, 22 Jun 72, by Paul J. Reiff.

During this quarter, testing of a new braking and stopping method for the high speed carriage return was continued. Wiring of the character generator has been completed. A method of mounting has been worked out that will have the circuits more easily accessible for servicing. The converter has been modified to accept parallel signals from punched paper tape. The circuits have been designed and their construction is 50% completed. (Author)

A program to develop programming and logic techniques combined with advanced packaging is described. All phases of the program are detailed including complete technical information describing the final model and its operation. The three stored programs have been successfully implemented and were demonstrated by use of the digit display and Flexowriter readout. Final testing included the full environmental range of +10 C to +40 C in accordance with system requirements. (Author)

Oregon State University has designed and constructed a medium speed, serial digital computer using glass delay lines circulating at 22 mc. as memory. The design objectives as originally conceived in a special seminar were: (1) To be a research project in computer design. (2) To be used as an educational machine. (3) To have easily modifiable hardware for basic research in computer systems design. An unusual arrangement of information within the 22 mc. memory allows a simple interface with the 340 kc. arithmetic unit, which results in an effective zero latency time and provides possibilities for an associative memory. The arithmetic unit has a command structure similar to large parallel machines and uses flip-flop arithmetic and control registers throughout. All hardware development has been aimed toward the concept of easy modification, elaborate console controls for effective man-machine interaction, and low cost. This report describes the status of the project as of August 21, 1967. (Author)

A medium speed, serial digital computer was constructed using glass delay lines circulating at 22 mc. as memory. An arrangement of information within the 22 mc. memory allows a simple interface with the 340 kc. arithmetic unit, which results in an effective zero latency time and provides possibilities for an associative memory. The arithmetic unit has a command structure similar to large parallel machines and uses flip-flop arithmetic and control registers throughout. All hardware development has been aimed toward the concept of easy modification, elaborate console controls for effective man-machine interaction, and low cost. (Author)

The depth recorder described was designed for the direct computer processing of data, which it provides in digital form on perforated tape. It is intended as a supplement to the Precision Depth Recorder installed on the Centre's Research Vessel.

Improvement of existing pulsejet engines resulted in engines having (1) a 425-fps design speed with a maximum over 500 fps, (2) a design-speed life exceeding 41 hr, (3) a 444-g design-acceleration loading with a maximum over 575 g, and (4) a specific thrust of 2.23. An analysis indicated that a 25% greater thrust is possible with a ducted engine at a 550-fps tip speed. Acoustic coupling of 2 engines with proximate tailpipes reduced the fundamental-frequency noise level. Exhaust-shroud design requirements were established for shrouds which enhance acoustic coupling and which do not adversely affect static performance. Opposed-engine configurations further reduced the noise level and favorably affected performance. The inlet noise level was not reduced by acoustically coupling /4 ducts. A capacitance-type pressure pickup with a 1.25- mc carrier frequency and a 50-psi maximum was used with a high-impedance probe to determine engine-pressure variations. Average inlet-valve operating temperatures of 145 deg F may permit the use of strain gages as inlet-valve position indicators. Inlet-valve natural frequency and damping characteristics could not be determined with commercial vibration equipment. Studies of electrical analogies for engine analysis provided (1) a basic circuit demonstrating the analogous behavior of electrical circuits and pulsejet engines, (2) a relaxation oscillator providing repetitive analogy operations and simulating combustion, (3) an artificial electrical line simulating acoustic resonant characteristics, and (4) a determination of engine-tube resonant modes.

The relaxation oscillations are investigated which occur when gas- filled voltage-regulator tubes are operated in parallel with a condenser, and a qualitative description of their mechanism is presented. The voltage across the tube as a function of current has a minimum; if the current through the tube is greater than that at the voltage minimum, then relaxation oscillations do not occur. A 100-Omega resistance in series with a VR105 tube reduces the tube current required to prevent oscillations. Sinusoidal oscillations were observed. The equivalent inductance of a VR105 increased with decreasing tube current and decreasing frequency.

A description is given of three pulse generators which produce related waveforms used in the control of a directly coupled logic system. The directly coupled transistor logic (DCTL) technique is first expounded in so far as it is relevant to the material in the text. Each generator is considered first in general terms complete with the associated logic diagrams, and then a detailed description is given of the practical interpretation illustrated with schematic diagrams and waveforms.

Preliminary experiments on treating cleaved lithium fluoride surfaces with Dri-Film (alkyl chloro silane) vapor to produce a surface that will inhibit spin relaxation were not successful as judged by the failure of water droplets to exhibit a large angle of contact on the treated surface. Other types of Dri-Film or other kinds of surfaces such as Teflon or wax have not yet been tried. It is intended to make direct re laxation measurements for oriented hydrogen atoms rather than rely on the water droplet test, which may not be suitable since LiF is very hygroscopic.

The report describes a simple method for developing computer models for digital and analog integrated circuits. The models are capable of allowing computer prediction of both normal performance and performance when the devices are exposed to gamma and neutron radiation environments. Device models have been developed for two NAND gates, two flip-flops, one four-bit Shift Register, a Monostable Multivibrator, an AND-OR-INVERTER, and two operational amplifiers. All models are demonstrated to agree with observed laboratory performance for conditions of pulsed gamma radiation of 3 x 10 to the 10th power rads (Si)/ Second. Neutron fluence levels of 1.2 x 10 to the 14th power neutrons per square centimeter, as well as non-radiation conditions. The 'black box' technique is employed for model development. The model descriptions were developed for use with the SCEPTRE circuit analysis program.

An inverter utilizing the silicon-controlled rectifier, capable of generating high power at high frequency, is described. A brief theoretical summary of the operation of the device is included, followed by an analysis of the inverter. Design procedures and graphs are developed that make possible the design of such an inverter based upon design criteria. An experimental model for operation at 15 kc was designed and tested. Results indicated that approximately 500 w of power can be obtained with this particular model. (Author)

The patent relates generally to relaxation oscillator circuits, and more particularly to an improved relaxation oscillator circuit wherein the effective RC time constant which determines the period of oscillation of the relaxation oscillator is many times greater than the actual RC time constant of the current limiting resistor and the charging capacitor.

Supersedes AD-287 526.

The article discusses the application of complementary transistor pairs in switching circuits and the lower limits imposed on the performance by a deterioration of the transistor characteristics. These are a reduction in gain at lower values of the d.c. emitter current and a reduction in speed in the small current region of operation. Several multivibrator circuits with two transistors are shown and analyzed. These include a regenerative circuit, a Schmitt trigger, astable and monostable multivibrators in the basic and in the Darlington versions, and more sophisticated cascade circuits with inverters. To this category belong logic circuits such as a NAND gate with CRDTL components, a universal logic, as well as monostable, astable, and bistable multivibrators - all using complementary pnp-npn transistor pairs also in their inverter stages. (Author), Edited trans. of Elektronika (Poland) v11 n7/8 p296-300 1970.

The purpose of the 1000 Megabit Per Second Pulse Gated Binary Modulation (1000 Mb/s PGBM) laser transceiver electronics was to design, develop, and test transmitter and receiver electronics suitable for use in a 1000 Mb/s PGBM Mode-locked Laser Communication System. The hardware was developed with the following primary objectives: (1) The system will handle either two 500 Mb/s channels of synchronous input data or three channels (492 Mb/s, 246 Mb/s, and 246 Mb/s) of asynchronous data; (2) The data reconstruction circuitry is capable of near optimum detection of Poisson modulated 1000 Mb/s return-to-zero (rz) data; (3) An optical link simulator is provided for the electronics transceiver test; (4) High speed data sources and error detectors are included for system performance measurements. The approach in the development of this hardware was to utilize a versatile line of previously developed high speed, low power hybrid circuitry in the design of all essential components. The circuit design and layout was organized such that the system feasibility for future flight usage was well demonstrated as was future expansion capability. When tested with the optical link simulator and additive Gaussian noise, the transceiver bit error rate performance was 1.5 dB from theoretical for both synchronous and asynchronous modes of operation.

The purpose of the contract is to develop the theory and methods required to fabricate microcircuit ultra high speed prescalers or divide-by-five counters capable of operating reliably from 225 to 400 MHz and to design, fabricate, test, and deliver 20 operational units with complete characterization of their static and dynamic electrical parameters, including transmission line requirements. A full monolithic approach will be used to provide the highest reliability and low cost (when produced in large quantities). At least one flip flop of the prescaler will be capable of counting reliably from 225 to 400 MHz. The applications for these prescalers will include integrated uhf frequency synthesizers, digital matched filters, and high speed LSI counters. (Author), See also Report dated 20 Oct 69, AD-864 103.

This report covers the design and fabrication of a flare firing intervalometer. The entire system was designed and fabricated in-house by the Solid State Applications Section at Rome Air Development Center. The case was designed and made in the Experimental Fabrication Shop. Most of the steps during the study, design, and fabrication are discussed, even though later knowledge and experience led to modification or to alternate approaches. The intervalometer was tested at the U.S. Army Limited War Laboratory, Aberdeen Proving Ground, Maryland. (Author)

The report describes the work completed to develop the theory and methods required to fabricate 20 microcircuit ultra high speed prescalers or divide-by-five counters. The prescalers are to operate reliably from 225 to 400 MHz. A second experiment is comprised of four MECL III flip-flops on a single monolithic die, interconnected using three layer metallization, to form the divide-by-two, divide-by-five function. Parts which were processed using both the standard MECL III process and the newer higher speed process were evaluated and the results are given in this report. Layout and ruby-cutting for the final monolithic prescaler was completed. (Author), See also Report dated 20 Jul 69, AD-860 054.

DISIM is a digital circuit simulator programmed to aid the engineer check his design. The circuit is described to the computer in terms of the basic gates and flip-flops and submits the description and some control cards to the computer. The circuit values are calculated and the desired ones are presented in a chart or a plot. This report describes the DISIM language and explains its use. (Author)

This report describes the design and operation of a prototype digital range and airframe-separation programmer (RASP) designed, built, and tested by the Naval Ordnance Test Station, China Lake, for use with the ASROC missile. RASP is that portion of the ASROC ignition and separation assembly (ISA) which programs target range and airframe separation for payload delivery to a point where an enemy submarine has been spotted. The payload is a torpedo attached to a parachute. Prior to launch, the velocity, needed for the missile to attain the range of the target, and the airframe-separation actuation time are computed and programmed into the RASP. The RASP integrates acceleration to obtain the velocity needed for thrust cutoff and also initiates airframe separation and ISA jettison when the programmed time has elapsed, thus deploying the parachute and lowering the torpedo into the water. The digital RASP is being developed as a possible replacement for the analog RASP currently used with ASROC. (Author)

The report presents a combined manual and computerized analysis of a 10 volt switching regulator. The regulator functions as a voltage-to-frequency converter utilizing a combination of frequency and pulse-duration modulation. (Author)

The report examines cryoelectric device, array, and assembled system considerations in the context of a postulated one million cell (one billion gate) Association Storing Processor (ASP) application (concept developed by Savitt, Love, and Troop). Cryotron and STD (Superconducting Tunneling Device based on the dc Josephson effect) devices are compared. Arguments based on practical array complexity, interconnection, and the necessary fault tolerant provisions are cited. Prerequisites to subsequent development of high complexity cryoelectric systems are apparent. (Author)

Those systems which are set up with semi-conductor elements are being used more frequently to solve various logical problems in the automation of industrial equipment. In the case of those systems which are program-controlled, the problem arises of relaying the information to the appropriate control element after it has been picked up by the detector and transmitted to the storage element, and to do this as directed by the program. The occurrence of events in a series is picked up by detectors and transmitted by a pulse. The information on occurrences is stored in a memory system composed of storage elements, and-gates, and or-gates. At the call signal, the information is transferred to the appropriate control elements in the order of arrival. For the storage of information consisting of n events, n squared pieces of storage elements are required to carry the sequence., Edited trans. of Meres es Automatika (Hungary) v14 n2 p51-55 1966, by D. Grandjean.

The research was initiated to develop solid state switching components for aircraft electric power systems, to perform developmental evaluations on the components, and to develop procurement type military specifications for each component. This report pertains only to the signal source. (Author)

The present article outlines the theory of the N-channel filter and reports the results of tests designed to study the basic properties of the filter. The new method of band filter synthesis described has the advantage that a deep pass-filter becomes converted into a band filter. It can be electrically tuned by changes in the frequency of the control pulse generator. At the same time, the shape of the passband curve remains unchanged. The authors conclude with the remark that in view of the existence of the side registers and other necessary auxiliary circuits all conditions are satisfied for a successful use of the above mentioned N-channel filters within the framework of solid state circuit technology. (Author), Edited machine trans. of Nachrichtentechnik (German Democratic Republic) n8 p323-7 1965.