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A compact MOSFET-C floating/grounded meminductor emulator (MIE) model is presented for high operating frequency and low power operation. The proposed MIE uses only 22 MOSFETs and two capacitors. Its performance is theoretically analyzed and rigorously verified using the Cadence Virtuoso software and hardware prototypes. The proposed MIE operates appropriately for a wide range of frequencies up to 5 MHz with $590 \mu \text{W}$ power consumption at a 180nm CMOS technology node and manifests important signature properties. The MIE layout area in 180 nm CMOS technology is $13107.5 \mu \text{m}^{2}$. To analyze the effects of statistical variations in MIE elements, extensive Monte Carlo simulations have been performed to demonstrate the robustness of the proposed MIE. For experimental validation, hardware prototypes have been developed and tested successfully. An MIE-based adaptive learning neuromorphic circuit is presented to show that it can mimic the behavioral responses of amoeba under varying environments such as temperature. [ABSTRACT FROM AUTHOR]

The performance of the power converter bus bar is not only determined by its normal operational design, but also related to its fault ride-through ability consideration. Conventional busbar design only takes the normal operational performance into account. This article proposes an optimal busbar design method for the modular multilevel converter (MMC) submodule, which takes both the normal and fault ride-through performance into account. The normal operational design is to realize low stray inductance and balanced inductance distribution between parallel capacitor branches. The basic structural design guideline for the MMC submodule is presented. Taking both the stray inductance and manufacturing cost into account, the optimal layout of the busbar is proposed. To balance the capacitor branch currents, the mathematical model of the busbar stray inductance is built. The influence of different busbar structures on the stray inductance is analyzed. The analysis is verified by simulation results. To improve the fault ride-through capability, special consideration is taken into account to reduce the thermal and mechanical stress at the weakest point. Simulation and experimental results verify the efficacy of the proposed approaches. [ABSTRACT FROM AUTHOR]

Parallel transmission (pTX) techniques are required to tackle a number of challenges, e.g., the inhomogeneous distribution of the transmit field and elevated specific absorption rate (SAR), in ultra-high field (UHF) MR imaging. Additionally, they offer multiple degrees of freedom to create temporally- and spatially-tailored transverse magnetization. Given the increasing availability of MRI systems at 7 T and above, it is anticipated that interest in pTX applications will grow accordingly. One of the key components in MR systems capable of pTX is the design of the transmit array, as this has a major impact on performance in terms of power requirements, SAR and RF pulse design. While several reviews on pTX pulse design and the clinical applicability of UHF exist, there is currently no systematic review of pTX transmit/transceiver coils and their associated performance. In this article, we analyze transmit array concepts to determine the strengths and weaknesses of different types of design. We systematically review the different types of individual antennas employed for UHF, their combination into pTX arrays, and methods to decouple the individual elements. We also reiterate figures-of-merit (FoMs) frequently employed to describe the performance of pTX arrays and summarize published array designs in terms of these FoMs. [ABSTRACT FROM AUTHOR]