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This paper introduces a novel, cost-effective solution designed to achieve large absorption bandwidth within the THz spectrum employing a miniaturized, single-layer metamaterial structure. The designed structure features a single circular ring composed of an ohmic resistive sheet with notably higher sheet resistance than traditional metallic resonators. This distinctive design is implemented on a lossy dielectric polyimide substrate with a backing of metallic gold. Our developed absorbing structure demonstrates the capability to achieve a substantial absorption bandwidth ranging from 3.78 to 4.25 THz, maintaining a consistent absorption rate of over 90%. Moreover, we conducted an analysis to assess its absorption performance under various sheet resistance values within the top layer. Additionally, we characterized its angular stability and polarization insensitivity through oblique incident and polarization angle analysis. Finally, an RLC circuital and interference theory approach is adopted to justify its simulated results. The proposed absorber shows potential for a broad spectrum of applications, encompassing communication, imaging, and diverse integrated circuits operating within the THz band. [ABSTRACT FROM AUTHOR]

This paper explores the influence of temperature on the scattering mechanism of multilayer graphene nanoribbon (MLGNR). A thermally aware electrical ESC model along with mathematical computations is presented for evaluating the parasitic and reports the performance analysis dependent on temperature of the MLGNR at global interconnect length for 16 nm, 22 nm, and 32 nm nodes of technology in terms of power dissipation, delay, and power delay product (PDP). It was examined that with rising temperature, there is a strident decrease in the mean free path of GNR interconnect, which further influence its own resistance at variable global lengths (500‒2000 μm) for all three technology nodes. The simulation program with integrated circuit (SPICE) emphasis simulation tool is used to estimate and compare the performance of MLGNR in terms of power dissipation, signal delay and PDP for three different nodes of technology. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (2000 μm) over a temperature range of 200 to 500 K for deep submicron technology nodes (16, 22, and 32 nm). Further, based on ITRS 2013, the analytical and simulated results are obtained at global interconnect length (2000 μm) for 16 nm technology node in the 200–500 K temperature range of MLGNR. The simulation and analytical results show that the outcomes of the two models are very similar. The models' trends show an increase in delay with increasing temperature levels (200‒500 K) 16 nm technology node. [ABSTRACT FROM AUTHOR]

The paper presents the results of thermal modeling of a half-bridge monolithic integrated circuit (IC) with integrated drivers and enhanced mode power high electron mobility transistors, based on a GaN-on-SOI heterostructure. It had been established that the main heat sources in the IC were the half-bridge GaN HEMTs. The heat from the half-bridge GaN HEMTs propagates in the chip and leads to heating of the logic block and gate drivers. Heating of half-bridge GaN HEMTs leads to increased channel resistance and IC output current drop. Heating of the gate drivers reduces driving current, as a result, increases the switching time of the half-bridge GaN HEMTs. Heating of the logic block increases the rise and fall times of the generated control signals, which worsens the dynamic characteristics of the IC. A comparative analysis of heat propagation for IC dies based on GaN-on-SOI and GaN-on-Si heterostructures showed that GaN-on-SOI structure has a 40% greater junction-to-backside thermal resistivity compared to GaN-on-Si structure. In this case, the specific thermal resistance in the direction of heat propagation from the hotspot of the transistor to the backside of the die for the GaN-on-SOI structure is almost two orders of magnitude greater than in the direction of its propagation to the frontside of the chip. The results obtained were used for IC layout optimization. The rearrangement of GaN-on-SOI IC functional blocks, as well as to introduction of additional heat-spreading elements on the frontside of chip were carried out during the optimization. [ABSTRACT FROM AUTHOR]

Semiconductor wafer manufacturing relies on the precise control of various performance metrics to ensure the quality and reliability of integrated circuits. In particular, GaN has properties that are advantageous for high voltage and high frequency power devices; however, defects in the substrate growth and manufacturing are preventing vertical devices from performing optimally. This paper explores the application of machine learning techniques utilizing data obtained from optical profilometry as input variables to predict the probability of a wafer meeting performance metrics, specifically the breakdown voltage (Vbk). By incorporating machine learning techniques, it is possible to reliably predict performance metrics that cause devices to fail at low voltage. For diodes that fail at a higher (but still below theoretical) breakdown voltage, alternative inspection methods or a combination of several experimental techniques may be necessary. [ABSTRACT FROM AUTHOR]

Recently, interest in programmable photonics integrated circuits has grown as a potential hardware framework for deep neural networks, quantum computing, and field programmable arrays (FPGAs). However, these circuits are constrained by the limited tuning speed and large power consumption of the phase shifters used. In this paper, we introduce the memresonator, a metal-oxide memristor heterogeneously integrated with a microring resonator, as a non-volatile silicon photonic phase shifter. These devices are capable of retention times of 12 hours, switching voltages lower than 5 V, and an endurance of 1000 switching cycles. Also, these memresonators have been switched using 300 ps long voltage pulses with a record low switching energy of 0.15 pJ. Furthermore, these memresonators are fabricated on a heterogeneous III-V-on-Si platform capable of integrating a rich family of active and passive optoelectronic devices directly on-chip to enable in-memory photonic computing and further advance the scalability of integrated photonic processors. Photonic integrated circuits have grown as potential hardware for neural networks and quantum computing, yet the tuning speed and large power consumption limited the application. Here, authors introduce the memresonator, a memristor heterogeneously integrated with a microring resonator, as a non-volatile silicon photonic phase shifter to address these limitations. [ABSTRACT FROM AUTHOR]

Encryption chips are specialized integrated circuits that incorporate encryption algorithms for data encryption and decryption, ensuring data confidentiality and security. In China, the domestic SM4 algorithm is commonly utilized, as opposed to the international AES encryption algorithm. These widely implemented encryption standards have been proven to be difficult to crack through crypt analysis methods Currently, power consumption side-channel attacks are the most prevalent method. They involve capturing power consumption data during the encryption process and subsequently recovering the encryption key from this data. The two leading methods are Differential Power Analysis (DPA) and machine learning techniques. DPA does not necessitate prior knowledge but relies heavily on the number of power consumption curves. With only 50 power consumption data points, the accuracy is a mere 80%. Machine learning methods require prior knowledge, achieving an accuracy rate above 95% with only 30 power traces, albeit with training times typically exceeding 15 min. In this paper, a distributed energy analysis attack approach was presented based on Correlation Power Analysis (CPA). The power consumption data was divided into 16 subsets, with each subset corresponding to 8 bytes of the key. By training each subset separately, the 8-byte key's corresponding power consumption data is reduced to only 100 dimensions, resulting in a 76% decrease in cracking time and a 3% improvement in cracking accuracy rate.This article also trains a more complex 256 classification model to directly crack the final key, achieving a success rate of 28% in cracking 128-bit passwords with only 1 power trace [ABSTRACT FROM AUTHOR]

This paper introduces a novel, cost-effective solution designed to achieve large absorption bandwidth within the THz spectrum employing a miniaturized, single-layer metamaterial structure. The designed structure features a single circular ring composed of an ohmic resistive sheet with notably higher sheet resistance than traditional metallic resonators. This distinctive design is implemented on a lossy dielectric polyimide substrate with a backing of metallic gold. Our developed absorbing structure demonstrates the capability to achieve a substantial absorption bandwidth ranging from 3.78 to 4.25 THz, maintaining a consistent absorption rate of over 90%. Moreover, we conducted an analysis to assess its absorption performance under various sheet resistance values within the top layer. Additionally, we characterized its angular stability and polarization insensitivity through oblique incident and polarization angle analysis. Finally, an RLC circuital and interference theory approach is adopted to justify its simulated results. The proposed absorber shows potential for a broad spectrum of applications, encompassing communication, imaging, and diverse integrated circuits operating within the THz band. [ABSTRACT FROM AUTHOR]

The growing complexity of integrated circuits (ICs) brings expensive manufacturing test cost. Adaptive testing becomes an important way to save test cost by predicting die quality to reduce the actual test content. However, reducing test items often results in unacceptable levels of test quality degradation. An adaptive testing method is proposed in the paper to reduce test cost while guaranteeing test quality. Two quality predictors are trained with a subset of test items and spatial information for subsequent decisions. The dies are clustered according to the prediction results, and the clustering results are graded. The distribution of the different grade classes determines the die quality of each grade. Experimental results using fabricated wafers and the associated test data show that the proposed method reduces more than 42% of test items, and can achieve better test quality, reducing test escapes and yield losses by more than 90% in the Circuit Probing test (CP). [ABSTRACT FROM AUTHOR]

This paper continues the research on the circuit synthesis problem for a multiplexer function of logic algebra, which is a component of many integrated circuits and is also used in theoretical study. The exact value of the depth of a multiplexer with select lines in the standard basis is found under the assumption that the conjunction and disjunction gates are of depth 1 and the negation gate is of depth 0; the depth equals if . Thus, it follows from previous results that the exact depth value equals for all positive integers such that either or . Moreover, for , this value equals 2, and for , it equals either or . Similar results are also obtained for a basis consisting of all elementary conjunctions and elementary disjunctions of two variables. [ABSTRACT FROM AUTHOR]

This paper reports the design and numerical results of three new extremely compact and efficient flat-top band-pass plasmonic filters operating in the near-infrared region. The proposed structures are realized in metal–insulator-metal plasmonic waveguides based on stub, tilted T-junction and right-angle trapezoid configurations. A built-in parameterized genetic algorithm is applied to maximize the transmission efficiency, while at the same time contributing to shrinking down the size of the device structures. It is shown that the tunability of the optical filters can be realized by modulating their structural parameters to gain control over the band-pass filtering wavelengths. Numerical calculations are conducted based on the finite element method of CST Microwave Studio and demonstrate that the suggested ultra-compact plasmonic waveguide filters offer wide bandwidths of more than 270 nm, 424 nm, and 289 nm, with transmission efficiencies of higher than 80%, 74.2%, and 74.3%, respectively. The sizes of the proposed wavelength filters are 490 nm × 575 nm, 350 nm × 180 nm, and 420 nm × 150 nm, respectively, which make them attractive candidates for applications in high density photonic integrated circuits (PICs). As a result, because of the promising characteristics of the proposed topologies such as their high efficiency, compact size, tunability, and simple structure they may find applications in on-chip integration, laser technology, and multi-photon fluorescence. [ABSTRACT FROM AUTHOR]

In this paper, ultra-compact, high isolation-ratio optical isolators for use in wavelength-division multiplexing networks are presented. The isolator is composed of two parts, including a straight waveguide and a resonator. The performance of the isolator is investigated for two kinds of disk and ring resonators. The structure is based on the metal–insulator–metal configuration in which the metal parts are of gold and the insulator parts are of a magneto-optical material. The effecting parameters, including the dimensions of the disk/ring resonator, the gap between the waveguide and the resonator, and the waveguide material are comprehensively studied using the finite-difference time-domain method. By changing the geometrical variables and materials, the isolation ratio of the disk-and ring-based isolators can reach up to 33.47 dB and 29.06 dB, respectively. The footprint of both isolators is less than 1 μm2. The proposed isolators can be used in photonic integrated circuits due to their ultra-compact footprint, high isolation ratio, and CMOS-compatible structures. [ABSTRACT FROM AUTHOR]

Silicon (Si) waveguide crossing serves as an enabling technology for dense Si photonic integrated circuits. Efficient crossing designs significantly boost the performance of photonic devices with many crossings. In this paper, several fundamental optical logic functions, such as XOR, AND, OR, NOT, NOR, NAND, and XNOR, are reported at 1550 nm telecom wavelength using direct Si waveguide crossing. The proposed scheme is made up of three input waveguides and one output waveguide arranged in the shape of the symbol ' + ' with a microring resonator in the middle. The operation of the specified logic functions depends on the constructive and destructive interferences generated by the phase differences between the incident optical beams. Using the contrast ratio and amplitude modulation metrics, the performance of the target logic operations is evaluated. Additionally, it is investigated and assessed how much the critical operating parameters affect the spectrum transmission. The proposed waveguide-based scheme can achieve better performance compared to other reported designs of similar nature, according to simulation outcomes derived using Lumerical FDTD. [ABSTRACT FROM AUTHOR]

Multiwavelength nanophotonic devices are essential components in photonic integrated circuits for on-chip all-optical signal processing applications with enhanced data-storage capacity and increased bandwidth. Wavelength demultiplexing is a widely used photonic processing function, required for photonic signal processing on compact silicon chip designs. In this paper, we study optical rainbow trapping in a line defect photonic waveguide, and propose to use that effect for demultiplexing the light at visible spectrum. A defect waveguide is created in graded-index photonic crystal (GRIN PC) structure (the structure is composed of Si- PC cylinders having gradually varying radii along one dimension) as main channel, which allows the rainbow-trapping along the waveguiding channel. Vertical (side) channels are introduced to the system for efficient wavelength demultiplexing with low crosstalks and high coupling efficiencies thanks to the fact that incident light is localized at different positions along the main channel for certain operating visible wavelengths of The corresponding inter-channel cross-talks of is obtained at these incident wavelengths, which strengthens the idea of using such a GRIN PC structure for efficient wavelength demultiplexing applications. The studied multichannel demultiplexing device is relatively compact with a footprint of , which could be fabricated via simple lithography processes on a single Si- wafer. As far as authors' knowledge, this is the first time in literature that GRIN PC waveguide is implemented for multichannel wavelength demultiplexing function. The proposed GRIN PC design could be implemented for color sensitive photo-detection, absorption enhancement and optical spectroscopy. [ABSTRACT FROM AUTHOR]

Many devices based on silicon and other photonic integrated circuit platforms exhibit significant polarization dependence. Polarization beam splitter (PBS) is a device that split optical signals into transverse electric (TE) and transverse magnetic (TM) modes. Among various PBSs, asymmetric directional couplers are widely used due to their fine performance, but their working bandwidth is limited due to wavelength changes that can lead to deviations in effective refractive index and coupling strength. We propose a PBS, which uses metamaterial anisotropy to replace structural asymmetry and break the bandwidth bottleneck. It achieves good performance in the wavelength range of 258 nm, where the extinction ratio of the TM polarization is greater than 24 dB and that of the TE polarization is greater than 26 dB. It covers the E, S, C, L, and U bands, and the coupling area is as small as 7.25×2.625 μm, with a total device footprint of 15.65×6.125 μm. [ABSTRACT FROM AUTHOR]

This paper proposes a symmetric plasmonic bandpass filter topology based on metal–insulator-metal waveguide configuration. The proposed filter is numerically simulated using the finite difference time domain method. Silver and air have been used as metal and dielectric materials in the proposed structure, respectively. The model used to characterize silver is Johnson and Christy. By the introduction of nanorods to the filter structure, the transmittance value can be improved. As a result, a maximum transmission peak of 93% is obtained. Other advantages of the proposed plasmonic filter include having a high Q-factor, a bell-shaped transmission spectrum, and being single-mode. Therefore, the proposed plasmonic bandpass filter can potentially be used in photonic integrated circuits. [ABSTRACT FROM AUTHOR]

This paper presents a novel compact low pass filter (LPF) based on spoof surface plasmon polaritons (SSPPs) with ultra-wide out-of-band suppression. The design utilizes a single-layer PCB with metal gratings in a tilted slotted stub shape on the top layer. The device size is 0.75λg×0.12λg\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$0.75\lambda _g \times 0.12\lambda _g$$\end{document} (λg\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$\lambda _g$$\end{document} denotes the guided wavelength). A lumped equivalent circuit model is also provided. Simulated results demonstrate excellent passband performance and impressive ultra-wide out-of-band suppression. A fabricated prototype confirms simulation findings, showing 1.1 dB insertion loss at the center frequency, reflection coefficient below -10 dB in the passband, and over 30 dB out-of-band rejection beyond 38 GHz. The proposed compact SSPP LPF exhibits significant potential for applications in high-performance, miniaturized integrated circuits within the microwave frequency ranges. [ABSTRACT FROM AUTHOR]

Localizing security-relevant hard blocks on modern System-on-Chips for physical attacks, such as side-channel analysis and fault attacks, has become increasingly time-consuming due to ever-increasing chip-area and -complexity. While this development increases the effort and reverse engineering cost, it is not sufficient to withstand resolute attackers. This paper explores the application of camera-based lock-in thermography, a nondestructive testing method, for identifying and localizing security hard blocks on integrated circuits. We use a synchronous signal to periodically activate security-related functions in the firmware, which causes periodic temperature changes in the activated die areas that we detect and localize via an infrared camera. Using this method, we demonstrate the precise detection and localization of security-related hard blocks at the die level on a modern SoC. [ABSTRACT FROM AUTHOR]

This paper investigates the capabilities of the resonant cavity system (ResCav) for detecting tampered integrated circuits (ICs) within supply chains. Prior research showcased ResCav’s ability to discern minor circuit variations, this study focuses on enhancing supervised classification results and introduces a one-class support vector machine (SVM) approach with a modified radial basis function kernel for novelty detection. Through finer hyperparameter tuning, the system achieves improved classification accuracy, demonstrating its potential to identify nuanced alterations with even higher precision and recall rates. Additionally, the application of a one-class SVM enables the detection of tampered ICs without reliance on labeled datasets, expanding utility in scenarios where access is limited to golden ICs. These advancements in ResCav’s capabilities signify progress in failure prevention methodologies, offering an efficient and non-destructive solution crucial for safeguarding against counterfeit and non-conforming components infiltrating critical supply chains. [ABSTRACT FROM AUTHOR]

In integrated photonic circuits, microring resonators are essential building blocks but are susceptible to phase errors due to fabrication imperfections and optical power fluctuations. Conventional active phase tuning methods are power-intensive and challenging to integrate into densely packed photonic chips. This study proposes a solution by integrating a thin 2D layer of In4/3P2Se6 (InPSe) onto silicon microring resonators (Si-MRR). This approach mitigates sensitivity to laser power and achieves non-volatile wavelength trimming. Under bias voltage, the device exhibits electro-optic behavior, offering a non-volatile phase trimming rate of −2.62 pm/V to −4.62 pm/V, corresponding to InPSe thicknesses of 45 nm to 120 nm. Low optical losses of 0.0091 to 0.0361 dB/μm were also measured, corresponding to thicknesses of 30 nm to 120 nm. The devices demonstrate stable in-situ resonance wavelength stabilization and bidirectional trimming, ensuring cyclic stability for non-volatile phase control. This advancement enhances the performance of silicon photonics across diverse applications, facilitating high-capacity, high-power operation in compact designs. [ABSTRACT FROM AUTHOR]

Photonic integrated circuits have been extensively explored for optical processing with the aim of breaking the speed and energy efficiency bottlenecks of digital electronics. However, the input/output (IO) bottleneck remains one of the key barriers. Here we report a photonic iterative processor (PIP) for matrix-inversion-intensive applications. The direct reuse of inputted data in the optical domain unlocks the potential to break the IO bottleneck. We demonstrate notable IO advantages with a lossless PIP for real-valued matrix inversion and integral-differential equation solving, as well as a coherent PIP with optical loops integrated on-chip, enabling complex-valued computation and a net inversion time of 1.2 ns. Furthermore, we estimate at least an order of magnitude enhancement in IO efficiency of a PIP over photonic single-pass processors and the state-of-the-art electronic processors for reservoir training tasks and multiple-input and multiple-output (MIMO) precoding tasks, indicating the huge potential of PIP technology in practical applications. Integrated photonic iterative processors provide a novel I/O-efficient computing paradigm for matrix-inversion-intensive tasks, achieving higher speed and energy efficiency than state-of-the-art electronic and photonic processors. [ABSTRACT FROM AUTHOR]

Controlling large-scale many-body quantum systems at the level of single photons and single atomic systems is a central goal in quantum information science and technology. Intensive research and development has propelled foundry-based silicon-on-insulator photonic integrated circuits to a leading platform for large-scale optical control with individual mode programmability. However, integrating atomic quantum systems with single-emitter tunability remains an open challenge. Here, we overcome this barrier through the hybrid integration of multiple InAs/InP microchiplets containing high-brightness infrared semiconductor quantum dot single photon emitters into advanced silicon-on-insulator photonic integrated circuits fabricated in a 300 mm foundry process. With this platform, we achieve single-photon emission via resonance fluorescence and scalable emission wavelength tunability. The combined control of photonic and quantum systems opens the door to programmable quantum information processors manufactured in leading semiconductor foundries. Integrating tunable quantum emitters with commercial photonic circuits is promising for quantum information applications but remains a challenge. Here the authors report integration of InAs/InP microchiplets containing quantum dot single photon emitters into a large-scale foundry silicon platform. [ABSTRACT FROM AUTHOR]

Patterns on polymers usually have different mechanical properties as those of the substrates, causing deformation or distortion and even detachment of the patterns from the polymer substrates. Herein, we present a wrinkling strategy, which utilizes photolithography to define the area of stress distribution by light-induced physical crosslinking of polymers and controls diffusion of residual solvent to redistribute the stress and then offers the same material for patterns as substrate by thermal polymerization, providing uniform wrinkles without worrying about force relaxation. The strategy allows the recording and hiding of up to eight switchable images in one place that can be read by the naked eye without crosstalk, applying the wrinkled polymer for optical anti-counterfeiting. The wrinkled polyimide film was also utilized to act as a substrate for the creation of fine copper circuit by a full-additive process. It generates flexible integrated circuit (IC) carrier board with copper wire density of 400% higher than that of the state-of-the-art in industry while fulfilling the standards for industrialization. Current wrinkling processes for pattern formation cannot be easily controlled, resulting in deformation or detachment of patterns from substrates. Here, Zhong et al. report a wrinkling strategy for creating patterned structures with long-range order and resistant to force relaxation. [ABSTRACT FROM AUTHOR]

This work consists of a design and simulation of a structure composed by an aluminum structural layer whose purpose is to act as an angular electrostatic micromotor. The structure of the micromotor is defined using the layers available from a 0.5 μm CMOS technology used for integrated circuit fabrication. In this proposal, a digital circuit is configured for the generation of the three phases needed for proper operation of the micromotor. The phases and poles of the stator are biased in an alternating sequence, thus, when there is a potential difference between the misaligned poles of the rotor and stator, an electrostatic force is generated that causes the motor to advance one step. If this sequence is performed correctly and periodically, the rotor reaches a set speed in a clockwise direction. As a novel contribution to the presented design, an FGMOS transistor is used as an auxiliary element to measure the rotating speed of the micromotor and whose control gate is a structure mechanically coupled to the rotor. The elements of the system are proposed for being monolithically integrated: the rotation control circuit, the micromotor, and the speed sensor. This work also shows a static simulation and a time-dependent simulation that allows predicting the behavior over time and the torque generated by the micro-actuator. [ABSTRACT FROM AUTHOR]

Semiconductors are an important electronic component and play a central role in many industrial fields, whose production system is spread all over the world, involving trade in many raw materials, mechanical equipment, and finished products. Comprehending a broad global production picture of the semiconductor industry can be an arduous task. To tackle this complexity, the social network analysis method was used to capture the flows of products between economies in the semiconductor industrial chain. This study analyzed the evolution of the trade pattern of four key commodities in the semiconductor industrial chain, with a focus on identifying the status of major economies in the global semiconductor trade system. Additionally, the influencing factors of the formation of the trade networks were explored by using the Exponential Random Graph Model. The results showed that: (1) From 2001 to 2019, the import and export trade pattern of four key commodities in the semiconductor industrial chain has shown the characteristics of "rising in the east and decreasing in the west", but the change range shows strong commodity heterogeneity, the change of the spatial pattern of integrated circuits trade is the most significant, and the integrated circuits trade proportion of Asian economies has increased hugely with more than 80%. (2) The trade connectivity of various commodities in the semiconductor industrial chain has increased, upstream support products with high technical requirements such as wafers and equipment have the lowest average degree and weak trade liquidity, and the average degree of trade network of packaging materials and integrated circuits is relatively high, with strong trade liquidity and closer and more prosperous trade connections. (3) From 2001 to 2019, the "core-periphery" system of global semiconductor industry trade has changed significantly, with the core circle undergoing obvious iterative reorganization. for example, China and Singapore have achieved status improvement to the core circle in the base materials trade network, while Malaysia has been squeezed into the semi-peripheral circle. (4) The formation of trade networks of various commodities in the semiconductor industrial chain was driven by three aspects: network self-organization, exogenous endowment attribute, and exogenous network embeddedness. Among them, the influence of the technological innovation level of economies on different commodity trade networks showed heterogeneous. [ABSTRACT FROM AUTHOR]

Topological domain structures have drawn great attention as they have potential applications in future electronic devices. As an important concept linking the quantum and classical magnetism, a magnetic Bloch point, predicted in 1960s but not observed directly so far, is a singular point around which magnetization vectors orient to nearly all directions. Here we show polar Bloch points in tensile-strained ultrathin ferroelectric PbTiO3 films, which are alternatively visualized by phase-field simulations and aberration-corrected scanning transmission electron microscopic imaging. The phase-field simulations indicate local steady-state negative capacitance around the Bloch points. The observation of polar Bloch points and their emergent properties consequently implies novel applications in future integrated circuits and low power electronic devices. Authors predict polar Bloch points with negative capacitance in tensile-strained ultrathin ferroelectric PbTiO3 film by phase-field simulations, observing their polarization structures by scanning transmission electron microscopic imaging. [ABSTRACT FROM AUTHOR]

In implantable electrophysiological recording systems, the headstage typically comprises neural probes that interface with brain tissue and integrated circuit chips for signal processing. While advancements in MEMS and CMOS technology have significantly improved these components, their interconnection still relies on conventional printed circuit boards and sophisticated adapters. This conventional approach adds considerable weight and volume to the package, especially for high channel count systems. To address this issue, we developed a through-polymer via (TPV) method inspired by the through-silicon via (TSV) technique in advanced three-dimensional packaging. This innovation enables the vertical integration of flexible probes, amplifier chips, and PCBs, realizing a flexible, lightweight, and integrated device (FLID). The total weight of the FLIDis only 25% that of its conventional counterparts relying on adapters, which significantly increased the activity levels of animals wearing the FLIDs to nearly match the levels of control animals without implants. Furthermore, by incorporating a platinum-iridium alloy as the top layer material for electrical contact, the FLID realizes exceptional electrical performance, enabling in vivo measurements of both local field potentials and individual neuron action potentials. These findings showcase the potential of FLIDs in scaling up implantable neural recording systems and mark a significant advancement in the field of neurotechnology. [ABSTRACT FROM AUTHOR]

Critical coupling in integrated photonic devices enables the efficient transfer of energy from a waveguide to a resonator, a key operation for many applications. This condition is achieved when the resonator loss rate is equal to the coupling rate to the bus waveguide. Carefully matching these quantities is challenging in practice, due to variations in the resonator properties resulting from fabrication and external conditions. Here, we demonstrate that efficient energy transfer to a non-critically coupled resonator can be achieved by tailoring the excitation signal in time. We rely on excitations oscillating at complex frequencies to load an otherwise overcoupled resonator, demonstrating that a virtual critical coupling condition is achieved if the imaginary part of the complex frequency equals the mismatch between loss and coupling rate. We probe a microring resonator with tailored pulses and observe a minimum intensity transmission T = 0.11 in contrast to a continuous-wave transmission T = 0.58 , corresponding to 8 times enhancement of intracavity intensity. Our technique opens opportunities for enhancing and controlling on-demand light-matter interactions for linear and nonlinear photonic platforms. The authors achieve enhanced cavity loading using complex-frequency excitations that can tailor on-demand the effective coupling rate in a microring resonator by precisely controlling the temporal evolution of the incident pulses. [ABSTRACT FROM AUTHOR]

In this work, a higher order-to-fundamental mode converter is reported and analyzed based on an asymmetric dual channel waveguide (ADC-WG) on silicon. In the reported structure, one of the two waveguides is infiltrated with nematic liquid crystal (NLC) material to add temperature tunability while the other one is a solid BK7 waveguide. The modal characteristics are obtained using the full vectorial finite difference method (FVFDM). In addition, the structural parameters and optical characteristics of the employed materials are investigated to achieve good wavelength selectivity with a short device length (LD). Thus, a compact mode converter that can work at different wavelengths including the telecommunication wavelength i.e., 1.55 μm with LD ~ 482.31 μm and a low crosstalk of − 19.86 dB is presented. To prove the thermal tunability of the suggested mode converter, its operation is tested through a temperature range between 20 and 35 °C and the results show that the mode conversion process is achieved at each temperature with different phase matching wavelengths (λPMW) but with quite similar coupling length (LC). The proposed device can therefore be effectively utilized in integrated photonic circuits. [ABSTRACT FROM AUTHOR]

Highlights: This review introduces the potential of 2D electronics for post-Moore era and discusses their current progress in digital circuits, analog circuits, heterogeneous integration, sensing circuits, artificial intelligence chips, and quantum chips in sequence. A comprehensive analysis of the current trends and challenges encountered in the development of 2D materials is summarized. An in-depth roadmap outlining the future development of 2D electronics is presented, and the most accessible and promising avenues for 2D electronics are suggested. Due to the constraints imposed by physical effects and performance degradation, silicon-based chip technology is facing certain limitations in sustaining the advancement of Moore's law. Two-dimensional (2D) materials have emerged as highly promising candidates for the post-Moore era, offering significant potential in domains such as integrated circuits and next-generation computing. Here, in this review, the progress of 2D semiconductors in process engineering and various electronic applications are summarized. A careful introduction of material synthesis, transistor engineering focused on device configuration, dielectric engineering, contact engineering, and material integration are given first. Then 2D transistors for certain electronic applications including digital and analog circuits, heterogeneous integration chips, and sensing circuits are discussed. Moreover, several promising applications (artificial intelligence chips and quantum chips) based on specific mechanism devices are introduced. Finally, the challenges for 2D materials encountered in achieving circuit-level or system-level applications are analyzed, and potential development pathways or roadmaps are further speculated and outlooked. [ABSTRACT FROM AUTHOR]