Search

Carrier phase‐shifted sine pulse width modulation is a common modulation strategy for medium‐ and low‐voltage cascaded H‐bridges (CHB). This paper proposes a novel jittered‐carrier phase‐shifted sine pulse width modulation (JCPS‐SPWM) to reduce the total harmonic distortion (THD) of the converter. It makes the carrier jitter regularly while the total switching times remain unchanged, which reduces the THD of the bridge arm voltage and current by moving the low‐order output harmonics of the bridge arm voltage and current to filterable high‐order harmonics. Since the total number of switching times remains unchanged, this modulation strategy will not cause any increase in switching loss. A seven‐level CHB simulation model and an experimental prototype are built to verify the effectiveness of the approach. The results show that harmonic content can be reduced by 47.5% compared with the traditional method, thus verifying the effectiveness of the JCPS‐SPWM. [ABSTRACT FROM AUTHOR]

The authors present the multi‐physical field performances comparative research for a 30 kW, 30,000 r/min high‐speed permanent magnet motor (HSPMM) when the motor is powered by the sinusoidal pulse width modulation (SPWM) voltage inverter and sinusoidal voltage source, respectively. Firstly, electromagnetic performances including torque, voltage and current of the HSPMM with different driving methods are compared and analysed by the finite element method (FEM). Considering the effects of high operation frequency, power losses of the HSPMM with different driving methods under full‐load conditions are calculated and compared with the skin effect and the proximity effect considered for HSPMM winding copper loss estimation. Based on the above analysis, a prototype driven by the SPWM voltage inverter is manufactured, with its electromagnetic and thermal performances tested and verified. In addition, several influencing factors of the HSPMM rotor eddy current loss are studied, with their effects on the HSPMM under different driving methods further analysed and compared as well. A novel equivalent power supply method is proposed to effectively save the calculation time with a negligible error. Finally, in order to further improve the heat dissipation capacity of the HSPMM, a novel cooling method is intensively studied with its influencing factors further analysed. The cooling effect of the novel cooling method and the temperature of the motor components are verified and calculated by the computational fluid dynamics (CFD) method. [ABSTRACT FROM AUTHOR]

A three‐level neutral point clamped (3L‐NPC) voltage source inverter (VSI) topology can be advantageous in electric vehicles with a high DC‐link voltage and a high switching frequency. A bulky DC‐link capacitor is not an option; thus, the DC‐link capacitor's sizing considering the traction system characteristics is an important design step. This paper investigates how the DC‐link capacitor size of a 3L‐NPC VSI gets affected by the combination of the interdependent characteristics of an electric drive, such as its power factor, modulation index, current, and fundamental frequency, with the effects of the modulation methods. Five pulse width modulation (PWM) methods, of which three of them have an active neutral point potential control, are compared in terms of their neutral point potential (NPP) oscillations. Then, the size of the DC‐link capacitor is determined for each PWM method so that the NPP ripple is kept under desired limits at all operating conditions. It is shown that both the modulation technique and the electric machine characteristics influence the capacitor size. For example, electric machine design modifications can introduce more than a 30% reduction in capacitor size. Finally, DC‐link and NPP oscillations with different PWM methods are experimentally validated in a scaled‐down 3L‐NPC inverter. [ABSTRACT FROM AUTHOR]

This paper proposes an extended state observer (ESO)‐based second‐order sliding mode control (SMC) for dynamic voltage restorers (DVRs). Unlike the conventional first‐order SMC and some second‐order SMC (SOSMC) methods that suffer from chattering, the proposed control method can alleviate chattering and achieve finite‐time convergence. Chattering suppression (i.e. eliminating discontinuities) is achieved via continuous control input which is also used to generate the pulse width modulation signals. However, while removing the discontinuities in the control input, the performance of the control method is degraded when it is subjected to disturbances. Therefore, an active disturbance rejection (ADR) based on an ESO is proposed to enhance the performance. In addition, an advanced single‐phase phase‐locked loop (PLL) using linear observer and quasi‐type‐1 PLL is also proposed. The effectiveness of the proposed method is verified through simulation and experimental results which are compared with the results of the existing SMC methods applied to DVR. [ABSTRACT FROM AUTHOR]

Among different types of transformerless photovoltaic inverters, multi‐level inverters based on switched‐capacitors (SC) are the burning topic of recent decades due to their potential advantages, such as, single source requirement, voltage boosting capability, and high power density. However, for a seven level output voltage, a conventional SC based inverter architecture uses more than two units of SC, a large amount of power switches, which then lead to capacitor voltage balancing problems. This paper presents a seven‐level switched‐capacitor transformerless inverter (SCTI), which is structured with only two SC units, ten power switches, and a single DC source. The proposed SCTI ensures voltage boosting capability, self‐voltage balancing, and low power semiconductor losses. Apart from these, a modified sinusoidal pulse width modulation (MSPWM) is also proposed in this work, which guarantees better thermal performance and low inverter output voltage THD for the proposed SCTI. The proposed SCTI along with the MSPWM is simulated in MATLAB/Simulink and PLECS computer simulation environments. A reduced scale laboratory prototype is also built and tested to ensure the feasibility of the proposed SCTI. [ABSTRACT FROM AUTHOR]

This study proposes a non‐isolated DC converter, which is connected in series with an inverter, with a high output voltage conversion ratio for application in electricity generation systems to upgrade low‐voltage to high‐voltage DC. The topology of the proposed converter is based on a boost converter, which has the limitation of a low voltage conversion ratio. The converter is developed and connected using a coupling inductance technique by adding a second winding L2 coupled with the prototype winding and diode D2. This technique increases the voltage ratio via the ratio operator (N) of both the induction coils by operating a single switch at a constant frequency of 60 kHz. The working principle of the proposed converter is based on pulse width modulation with a duty cycle ≤40%. When the converter receives a low voltage DC input of 36 V, it converts the input to a high output voltage of 325 V at an output power 125 W, showing a circuit efficiency of 92.48% at full load. The synthesis and design of the controller include a linear approach to represent the parameters using the small signal methodology, which is employed to establish a transfer function. Furthermore, the proposed converter is capable of effectively regulating the output voltage, even when subjected to variations in the output load by employing a proportional–integral control mechanism. The close loop results obtained from simulations and practical implementation verified the proposed circuit design, as both results agreed with the theoretical analysis. This paper presented the high output voltage conversion ratio non‐isolated DC converter, which would be applied in the electricity generation system from the substitute source, to upgrade the low‐voltage to the high‐voltage DC, then series connected with DC–AC inverter. The presented converter had the topology development from DC boost converter with the limitation of the low‐voltage conversion ratio, which was developed and corrected with the coupling inductance technique by adding the second winding L2 to coupling with the prototype winding and diode D2. This technique could increase the higher voltage ratio via the ratio operate (N) of both induction coils, with the operating of a single switch, at the constant frequency 60 kHz. It worked according to the pulse width modulation with the duty cycle ≤40%. This converter receives low voltage input 36 VDC provide to high voltage output 325 VDC, at the output power 125 W and the circuit efficiency equal to 92.48%, at the full load. And could maintain the output voltage by PI control under changing of output loading condition. According, it were found that the obtained close loop results from simulation and implementation results verified the proposed and design circuit. Both results agreed with the theoretical analysis. [ABSTRACT FROM AUTHOR]

In vehicle‐to‐grid (V2G) applications, a voltage source inverter (VSI) directly connects to a residential load or grid for DC/AC conversion and power flow control. In VSI, dead‐time is employed to prevent the breakdown of switching devices, however, the introduction of dead‐time leads to distortions of output voltage and current in both stand‐alone and grid‐tie modes. For the case of a power factor of 1, by analyzing the dead‐time effect of digital‐controlled double‐frequency sinusoidal pulse width modulation, a compensation amount is proposed to introduce in the modulation signals, the value of which is half of the delay register that generates a dead‐time of td. Moreover, considering the phase delay caused by hardware and software filtering in sampling, the grid‐tie mode control strategy based on dead‐time compensation is further proposed, which introduces the grid voltage as a feedforward signal. A 3.5 kW V2G experimental prototype is built and tested to verify the feasibility of the proposed strategies. The simulation and experimental results show that the proposed methods are effective for both modes, which improve the output distortion for different dead‐time without additional hardware circuits. [ABSTRACT FROM AUTHOR]

The authors propose a current fluctuation reduction strategy based on optimal three‐space‐vector pulse‐width modulation (TSVPWM), which is used to improve the service‐life of the dc‐link electrolytic capacitors in two‐level three‐phase voltage‐source inverter (VSI) system. Differing from the typical SVPWM‐based method that employs two adjacent active voltage vectors and zero voltage vectors to synthesise the reference voltage, the proposed strategy selects the required voltage vectors based on the minimum dc‐link electrolytic capacitor current fluctuation. With the proposed strategy, an objective function for the root‐mean‐square value of dc‐link electrolytic capacitor current is first constructed under the constraint of eight permissible voltage vectors. And then, by solving the minimum of the objective function through the piecewise linear programming, the optimal three voltage vectors under the different modulation ratios and load power factors are obtained accordingly, so as to achieve the minimum dc‐link electrolytic capacitor current fluctuations during each switching period. Meanwhile, a PWM implementation scheme based on positive–negative double carrier signals is presented, which not only simplifies the implementation process but also effectively reduces the switching losses of power devices. Finally, the experimental results demonstrate that the proposed strategy can minimise the dc‐link electrolytic capacitor current fluctuation under different working conditions. [ABSTRACT FROM AUTHOR]