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A novel inductance simulation circuit employing only two dual‐output voltage‐differencing buffered amplifiers (DO‐VDBAs) and a single capacitance (grounded) is proposed in this paper. The reported configuration is a purely resistor‐less realization that provides electronically controllable realized inductance through biasing quantities of DO‐VDBAs and does not rely on any constraints related to matched values of parameters. This structure exhibits excellent behavior under the influence of tracking errors in DO‐VDBAs and does not exhibit instability at high frequencies. The simple and compact metal‐oxide semiconductor (MOS) implementation of the DO‐VDBAs (eight MOS per DO‐VDBA) and adoption of grounded capacitance make the proposed circuit suitable for on‐chip realization from the perspective of chip area consumption. The function of the pure grounded inductance is validated through high pass/bandpass filtering applications. To test the proposed design, simulations were performed in the PSPICE environment. Experimental validation was also conducted using the integrated circuit CA3080 and operational amplifier LF‐356. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive study of Class‐‐E/F2 and inverse Class‐‐F power amplifiers (PAs) designed for 35–42 GHz millimeter‐wave applications, utilizing a 130 nm CMOS process. The proposed RF PAs are well suited for wide frequency‐band millimeter‐wave and 5G radio transmitters. A comprehensive study of limiting factors in amplifier efficiency is presented in this paper. The study encompasses an analysis of all the factors that restrict the efficiency of the switched power amplifier. The first proposed power amplifier is based on the Class E/F2 architecture, comprising a parallel capacitor, second harmonic resonance circuit, and output matching network. Conversely, the second suggested power amplifier is constructed using the inverse Class‐‐F topology, which includes harmonic termination and matching networks. The harmonic termination circuit incorporates a second harmonic resonance network and utilizes a parasitic capacitor to control the harmonic components. Both the proposed Class E/F2 and inverse Class‐‐F architectures are employed to reshape the drain current and voltage waveforms, aiming to reduce the overlap between them and, consequently, improve efficiency. The suggested power amplifiers comprise a driver Class‐‐AB stage and a power stage constructed based on either the Class E/F2 architecture or inverse Class‐‐F topology, utilizing harmonic termination networks at the output load. Two new designs of high‐Q factor on‐chip finger capacitors have been implemented to improve efficiency and radio frequency performance. Achieving input matching and inter‐stage matching is facilitated by employing two novel on‐chip transformers designed for maximum power transfer. Additionally, an inter‐stage matching inductor is utilized in a cascode configuration to enhance the overall RF performance. The on‐chip transformers, inductors, and finger capacitors are designed using the HFSS software program. S‐parameter files (SNP files) of the designed on‐chip components are extracted and inserted into the simulation tool to ensure accurate results. The proposed Class E/F2 power amplifier achieves a constant power of 14.9 dBm, an extreme power added efficiency (PAE) of 11.7%, and a maximum gain of 13.74 dB. In contrast, the suggested inverse Class‐‐F power amplifier attains a constant power of 15.4 dBm, a peak PAE of 12.6%, and a maximum gain of 14.8 dB. The DC power consumption is 73 and 66 mW for the proposed Class E/F2 and inverse Class‐‐F PAs, respectively, while their active sizes are 0.14 and 0.2 mm2. [ABSTRACT FROM AUTHOR]

Summary Oscillator‐based Ising machines (OIMs) particularly those realized in complementary metal oxide semiconductor (CMOS) have gained popularity for solving combinatorial optimization problems (COPs) in recent years due to its scalability, low‐power consumption, and room temperature operation. The implemented OIMs have thus far focused on solving optimization problems with a single global minima. However, real‐life optimization problems often have multiple solutions. In this paper, we propose a generalized approach to solve COPs with single (without contention), as well as multiple (with contention) solutions using frequency tunable CMOS ring oscillator (ROSC)‐based Ising machine. A capacitive frequency tunable CMOS ring‐oscillator coupled with an internal subharmonic injection locking (SHIL) generator realized using 14‐nm FinFET models works as Ising spin in the proposed approach. We demonstrate how frequency tuning can help in attaining good quality results and also determine all possible solutions of COP with contention. We also propose a generalized algorithm for monitoring the states of the oscillator network to indicate tuning necessity and extract solutions from the oscillator's output irrespective of the type of COP. [ABSTRACT FROM AUTHOR]

This paper presents a novel extended input voltage dynamic range (IVDR) amalgamate charge pump (CP) for energy harvesting systems. The proposed amalgamate CP adaptively switches its charge transfer transistor into switch and diode connection based on the input voltage, effectively enhancing the power conversion efficiency (PCE) over a wide input voltage range. Implemented in 65 nm CMOS technology, the post‐layout results demonstrate a PCE exceeding 40% within the input voltage range of 0.36–0.85 V, under 60 kΩ load. The design achieves an extended IVDR of 0.49 V with a peak PCE of 50.02% observed at an input voltage of 0.45 V. The proposed amalgamate CP design features two distinct charge transfer transistor connections, leveraging the strength of Dickson CP with low reversion loss in high input voltage range and the low conduction loss of cross‐coupled CP (CCCP) in low input voltage range, thereby extending the input voltage operation range of conventional CP. [ABSTRACT FROM AUTHOR]

Cu‐Sn transient‐liquid‐phase bonding has a limit in achieving small diameter/high‐density bumps due to the extrusion of the melted Sn layer during bonding. This paper report a new method that can fabricate small diameter Cu‐Sn bumps with 5 μm diameter and 25 μm pitch based on a new thermal reflow and pre‐bonding method that enables solid‐state Cu‐Sn reaction for avoiding Sn extrusion. Using the new method, 3D integration of a 640 × 480 MEMS array on a CMOS circuit chip has been demonstrated. This method can be used in 3D integration of MEMS arrays and CMOS circuits such as micromirror arrays. © 2024 Institute of Electrical Engineer of Japan and Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a vector‐sum phase shifter (VSPS) integrated with a wideband high‐gain low‐noise amplifier (LNA) for Ka‐band phased‐array receivers is presented. The digitally controlled VSPS based on the RF phase shifting architecture consists of a modified I/Q signal generator with additional inductor resonance and a programmable variable gain amplifier (VGA) based on Four 3 × 4 transistor arrays. Besides the reduced parasitic effect of the I/Q signal generator, an Equidistant Contraction Technology (ECT) is used in the VGA, to maintain higher phase shift accuracy of the VSPS. A multistage LNA with series inductor peaking is adopted to fulfill the flat wideband gain, where LC resonance networks are used as interstage matching to compensate for gain roll‐off at a higher frequency. Based on simulations in 65 nm CMOS technology, the presented LNA‐Phase shifter has achieved an average NF of 3.24–3.66 dB, and an average gain of 13.1–23.6 dB. Moreover, an RMS phase error of 1.1–12.6°, an RMS gain error of 4.2–5.6 dB, and an RMS magnitude error of 2.1–2.8 dB are maintained across 27–40 GHz, with a 360° phase shift coverage in steps of approximately 2.8125°. The chip consumes 16.83 mW from a 1.2 V supply voltage, and the occupied area is 0.65 mm2. [ABSTRACT FROM AUTHOR]

Digital RF technology has been developed and has been applied to below 6 GHz wireless applications. By replacing the IC die consumptive RF/analog circuit blocks by digital signal processor and circuit, digital rich/small transceivers can be realized. Since the foundation of this technology is based on the Nyquist theory, the operational frequency of the circuit has been limited by the Nyquist frequency (=1/2 of sampling clock frequency). As a result, the maximum operational RF frequency of existing digital RF technology was below 6 GHz. In this paper, a new direct digital RF technology that utilizes the higher‐order Nyquist zones is introduced. This technology enables handling RF signal in beyond Nyquist frequency range which means over 6 GHz range. The results of fabricated 26/28 GHz‐band transmitter/receiver are reviewed. Since the transceiver architecture with the proposed technologies does not require an RF local oscillator and up/down converters, it is suitable for microwave/millimeter‐wave multi‐antenna systems such as next generation satellite on‐board digital beam forming and Beyond 5G fully digital Massive multiple‐input multiple‐output systems. Key Points: Proposed direct digital RF transceiver technology utilizes the higher‐order Nyquist zones and mmW signal can be handled directlyDirect digital RF technology brings compact/digital rich mmW transceivers and will realize large scale digital beam forming antennas for mmW applications [ABSTRACT FROM AUTHOR]

A high gain D‐band hybrid integrated on‐chip antenna (OCA) based on a low‐cost printed circuit board (PCB) packaging technology is analyzed and designed in a standard 40‐nm CMOS process in this paper. The proposed OCA is a hybrid structure of a slotted patch OCA with off‐chip PCB ground and off‐chip dielectric resonator (DR). The proposed OCA exhibits a simulated gain of 3.5 dBi and 53% radiation efficiency at 150 GHz. The simulated impedance bandwidth is 20 GHz. The radiation performance and impedance bandwidth of the OCA are observably improved with the proposed techniques. The proposed OCA occupies 0.52 × 0.56 mm2, and addresses the highly desirable yet challenging overall design of future low‐cost integrated millimeter‐wave (mm‐Wave) and terahertz (THz) systems, which hit the mark on cost and compatibility. [ABSTRACT FROM AUTHOR]

Summary In the first part of this paper, we closely examine well‐known methods for balancing the output power level of the pseudo‐differential current‐reuse voltage‐controlled oscillator. We scrutinize their effectiveness in terms of canceling output mismatches, insensitivity to process, voltage, and temperature variations, and their capability of not degrading phase noise performance. Through analyses and simulations, it is shown that contrary to common belief, some techniques are not as effective as previously thought and should be employed only under specific circumstances. The best conventional approach is proven to be the use of a common‐mode shunting capacitor at the inductor's center tap node to create a virtual ground. In the second part, it is demonstrated that the current‐reuse voltage‐controlled oscillator can intrinsically produce balanced outputs without using any additional techniques or extra passive or active components. Using single‐ended tank capacitors instead of differential ones, the common‐mode voltage of the outputs is shunted to the real ground. This technique reintroduces a reference voltage to the tank circuit, forcing the oscillator to achieve equilibrium between positive and negative swings. The proposed current‐reuse oscillator is designed and post‐layout simulated in a 65‐nm CMOS process, covering a frequency range of 4.84–6.38 GHz with an average power consumption of 0.65 mW. It produces balanced outputs with an amplitude error of less than ±0.2% and achieves a phase noise of −126.7 dBc/Hz and FoMT of 201.8 dB at a 3‐MHz offset frequency. [ABSTRACT FROM AUTHOR]

A four‐stage CMOS operational amplifier is proposed in this work. The designed amplifier is frequency compensated via two differential blocks and two Miller capacitors. Unlike well‐known frequency compensation methods, the proposed compensation leaves the output node while exploiting extremely smaller capacitors compared to conventional approaches. The presented approach is modeled symbolically and realized at the circuit level via the Hspice circuit simulator and 0.18 μm CMOS technology. Good agreements between two separate simulation paths verify the validity and accuracy of the proposed approach. Ample simulation results are reported to investigate the proposed amplifier regarding parameter mismatches. According to the simulation results, the proposed four‐stage amplifier is an excellent candidate to be used in larger systems such as data converters, modulators, and sensors while it shows more than 169 dB as DC‐gain, 10 MHz as unity gain frequency with power consumption less than 500 μW. [ABSTRACT FROM AUTHOR]

Body implants play a crucial role in clinical applications, encompassing data acquisition, diagnosis, and disease treatment. However, challenges in size, power consumption, and biocompatibility, particularly in brain applications requiring small, battery‐free devices for deep areas, hinder their development. Despite potential advances through simplified, single‐purpose devices, such as recording or stimulation, overcoming the power and biocompatibility issues remains a hurdle. Addressing this, the article introduces an ultrasonically powered light delivery implant (LDI) utilizing lead‐free piezoelectric material (Li0.08K0.46Na0.46) NbO3 to harvest energy from external ultrasonic waves. The prototype includes a piezoelectric cube, a chip fabricated in 180 nm CMOS technology, and a microscale light‐emitting diode (μ‐LED) for optogenetics. Achieving an end‐to‐end efficiency of 0.75%, the LDI holds promise for various optogenetic studies, particularly in animal studies targeting specific brain areas for treating Parkinson's disease. The delivered optical power on the μ‐LED surface, at 14.1 mW mm−2, presents applicability to diverse studies involving specific opsins. [ABSTRACT FROM AUTHOR]