Search

This paper focuses on the digital closed-loop design for a step-up converter with hybrid switching. For this purpose, for the first time, the control-to-output small-signal transfer function of a hybrid switching converter is determined in the rational form. Based on it, a type 3 analog controller is designed, and then, its digitized counterpart is found, and the digital controller is designed using a digital signal processor. The closed-loop operation is then validated both through simulation and practical implementation. [ABSTRACT FROM AUTHOR]

This paper crowns efforts, made by its author, aiming in showing and proving that the current formula for calculation of the spectra of output signals at A/D converters requires a correcting factor in it. A number of partial results obtained and published in the last years are referred to here. They paved the way to a fully satisfactory and correct result; it is presented in this work. The corrected formula for spectrum calculation is derived using a description of the output signal of an A/D converter by means of the so-called Dirac comb, however not in a direct form, but with taking into account physical reality. In addition, the paper contains a number of interpretative remarks, comments, and explanations - clarifying those matters that have so far been omitted in analyses of the sampling process, despite the fact that they raised various types of doubts. [ABSTRACT FROM AUTHOR]

Eddy current inspection has been extensively employed in non-destructive testing of various conductive materials. The coil probe, as a mainstream sensor in the eddy current detection system, inevitably encounters interference from external signals while transmitting its own signal. Therefore, developing techniques to extract valuable signals from noisy ones is crucial for ensuring accurate detection. Carbon fiber composites not only possess significantly lower electrical conductivity compared to conventional metallic materials but also exhibit notable anisotropy. To address this issue, we designed an '8' coil probe set where the excitation coil does not electromagnetically interfere with the detection coil. However, practical applications that require portability and miniaturization pose challenges when utilizing this coil probe set to identify carbon content or defects due to the typically weak output signal. To address this issue, this paper proposes a design that combines the '8' structure of the planar coil probe with the principle of phase-locked amplification to create a dual-phase sensitive phase-locked amplification detection circuit. These specific design ideas were tested using a weak signal, which passed through the preamplifier, secondary amplifier, and band-pass filter comprising the target channel for signal amplification and noise filtering. The effective signal amplitude is proportional to the inverse phase difference between the direct current (DC) signal and inversely proportional to the amplitude of the signal. Finally, the DC signal was passed through an analog-to-digital converter (ADC). The analog-to-digital converter (A/D) is used to collect and calculate the DC signal, enabling the detection of weak electrical signals. Simulation experiments demonstrated that the signal detection circuit has an amplitude error below 0.2% and a phase error below 0.5%. The phase-locked amplification circuit designed in this paper can effectively extract the tiny impedance change signals of the planar coil sensor probe with high sensitivity and good robustness. [ABSTRACT FROM AUTHOR]

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A "sandwich" capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays' benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages. [ABSTRACT FROM AUTHOR]

This paper presents a design for timing mismatch calibration in a TIADC (Time-Interleaved Analog-to-Digital Converter) with wideband inputs. By exploiting the approximately linear relationship between the autocorrelation properties of sub-ADCs and timing mismatch, we achieve rapid convergence of error estimation. A low-cost detection method is proposed based on the convergent monotonicity of the Least Mean Square (LMS) algorithm, which can automatically correct the calibration direction when the input signal goes beyond the Nyquist zone. Physical test results indicate that the spurs caused by timing mismatch can be suppressed by 26–30 dB using the proposed method. [ABSTRACT FROM AUTHOR]

Wideband spectrum sensing with a high-speed analog-digital converter (ADC) presents a challenge for practical systems. The Nyquist folding receiver (NYFR) is a promising scheme for achieving cost-effective real-time spectrum sensing, which is subject to the complexity of processing the modulated outputs. In this case, a multipath NYFR architecture with a step-sampling rate for the different paths is proposed. The different numbers of digital channels for each path are designed based on the Chinese remainder theorem (CRT). Then, the detectable frequency range is divided into multiple frequency grids, and the Nyquist zone (NZ) of the input can be obtained by sensing these grids. Thus, high-precision parameter estimation is performed by utilizing the NYFR characteristics. Compared with the existing methods, the scheme proposed in this paper overcomes the challenge of NZ estimation, information damage, many computations, low accuracy, and high false alarm probability. Comparative simulation experiments verify the effectiveness of the proposed architecture in this paper. [ABSTRACT FROM AUTHOR]

This paper offers the first demonstration of the design and layout of a fully integrated power converter in a monolithic Silicon Carbide (SiC) technology. A 400 V Buck Converter integrated with Gate-Drivers and Low-Voltage Control circuitry in a 25–600 V Mixed-Mode SiC CMOS technology has been presented in this paper. A new SiC technology has been developed for this design which has a feature size of 1 μm. This technology allows integration of High-Voltage Power FETs and Low-Voltage CMOS circuits on the same die with a common substrate. Both high-side and low-side Power FETs are N-type hence a bootstrap circuit is used, and the gate drivers use an isolated capacitive level shifter to translate the signals from the 25 V domain to the 400 V domain which is the input voltage of the Buck Converter. The load current is 1 A and the nominal output voltage is 100 V thereby meaning that the output power is 100 W. The switching frequency is up to 1 MHz, and the duty cycle can range from 10% to 90% signifying a wide range of operation of the converter. [ABSTRACT FROM AUTHOR]

A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology. [ABSTRACT FROM AUTHOR]

As the current mainstream high-precision ADC architecture, sigma-delta ADC is extensively employed in a wide range of domains and applications. This paper presents the design of a highly efficient cascaded digital decimation filter for sigma-delta ADCs, emphasizing the suppression of high folding band noise and the achievement of a flat passband. Additionally, this study addresses the critical balance between filter performance and power consumption. An inserting zero (IZ) filter is incorporated into a cascaded integrator comb (CIC) filter to enhance aliasing suppression. The IZ filter and compensation filter are optimized using the particle swarm optimization (PSO) algorithm to achieve greater noise attenuation and smaller passband ripple. The designed filter achieves a noise attenuation of 93.4 dB in the folding band and exhibits an overall passband ripple of 0.0477 dB within a bandwidth of 20 KHz. To decrease the power consumption in the filter design, polyphase decomposition has been applied. The filter structure is implemented on an FPGA, processing a 5-bit stream from a 64-times oversampling rate and third-order sigma-delta modulator. The signal-to-noise ratio (SNR) of the output signal reaches 91.7 dB. For ASIC design, the filter utilizes 180 nm CMOS technology with a power consumption of 0.217 mW and occupies a layout area of 0.72 mm2. The post-layout simulation result indicates that the SNR remains at 91.7 dB. [ABSTRACT FROM AUTHOR]

The BC501A sensor is a liquid scintillator frequently used in nuclear physics for detecting fast neutrons. This paper describes a hardware implementation of digital pulse shape analysis (DPSA) for real-time analysis. DPSA is an algorithm that extracts the physically relevant parameters from the detected BC501A signals. The hardware solution is implemented in a MicroTCA system that provides the physical, mechanical, electrical, and cooling support for an AMC board (NAMC-ZYNQ-FMC) with a Xilinx ZYNQ Ultrascale-MP SoC. The Xilinx FPGA programmable logic implements a JESD204B interface to high-speed ADCs. The physical and datalink JESD204B layers are implemented using hardware description language (HDL), while the Xilinx high-level synthesis language (HLS) is used for the transport and application layers. The DPSA algorithm is a JESD204B application layer that includes a FIR filter and a constant fraction discriminator (CFD) function, a baseline calculation function, a peak detection function, and an energy calculation function. This architecture achieves an analysis mean time of less than 100 µs per signal with an FPGA resource utilization of about 50% of its most used resources. This paper presents a high-performance DPSA embedded system that interfaces with a 1 GS/s ADC and performs accurate calculations with relatively low latency. [ABSTRACT FROM AUTHOR]

This paper proposes an all-digital calibration algorithm that utilizes a reference channel to suppress the timing mismatch in the Time-Interleaved Analog-to-Digital Converter (TIADC). The output of the reference channel is aligned with each sub-channel in turn, therefore enabling the simultaneous sampling and conversion of the same input signal. First, the statistical characteristics across the channels are employed for estimating the timing mismatch; then, by comparing the output difference between the reference channel and the sub-channels that are sampled simultaneously, the deviation of the derivator can be calibrated. Finally, combining both calibration results yields an accurate final output. This proposed algorithm provides an effective solution to improve TIADC performance in high-speed data acquisition systems. The proposed architecture is applied to a 12-bit 2.4 GS/s four-channel TIADC model, and then its effectiveness is verified. The simulation results exhibit that the Effective Number Of Bits (ENOB) at an input signal frequency of 984 MHz shows a remarkable improvement from 6.88 bits to 11.92 bits. The effectiveness of this technique is also demonstrated through the off-chip calibration of a commercial 12-bit four-channel 2 GS/s TIADC using a 680 MHz input signal that is based on the actual chip results. [ABSTRACT FROM AUTHOR]

Successive approximation register (SAR) analog-to-digital converters (ADC) have the advantages of a simple structure, low power consumption and a small area compared with other types of ADCs, and thus, high-performance SAR ADCs have always been a hot research topic in the industry. In this paper, a 12-bit SAR ADC design with calibration using a hybrid RC digital-to-analog converter(RC DAC) structure is proposed to improve the conversion accuracy of the ADC and reduce the circuit area at the same time. The analog supply voltage and reference voltage of the ADC are 3.3 V, and the digital supply voltage is 1.2 V. The ADC adopts a mixed digital–analog design scheme, in which the internal comparator, latch, DAC capacitor array, etc., are analog parts, and the rest of the SAR algorithms and calibration algorithms are all implemented in digital Verilog code, with a conversion accuracy of 0.8 mV and a calibration accuracy of 0.5 LSB. The ADC can be selectively calibrated, and the simulation shows that the accuracy of the calibrated ADC can be guaranteed to be within 2 LSB under a 14 MHz digital clock with a sampling rate of 1 MHz. After simulation at a sampling rate of 1 MHz and an input frequency of 244 Hz sine wave, the effective bit count of the ADC is 9.54 bits and the SFDR is 63.71 dB. The circuit consumes 1.78 mW with a 3.3 V supply voltage. The overall layout core area is 411 μ m × 517 μ m. [ABSTRACT FROM AUTHOR]

The increasing demand for low voltage, power efficient, high-speed analog-to-digital converters (ADCs) results in the improvement of speed and power of regenerative dynamic comparator. In this paper, a dual-tail dynamic comparator is used with two extra transistors in the latch stage. These extra transistors help in the increase of transconductance of the latch stage, which helps decrease the delay of the proposed comparator. Mathematical analysis is done for the proposed architecture; this gives the idea of reducing the delay of the comparator with an increase in the transconductance of the comparator. The simulation and layout of the proposed comparator are done on the Cadence software with 90 nm CMOS technology. This proposed design is simulated with a 2 GHz clock frequency at supply voltage of 1 V. The proposed architecture consumes a power of 39.19 μ W and a delay of 143.12 ps at 1 V supply voltage, 5 mV input difference voltage and 0.9 V common mode voltage. The Monte Carlo simulation of the proposed architecture for power, delay, power delay product (PDP) and offset is also demonstrated in this paper. Process corner analysis is done for power, delay and PDP. [ABSTRACT FROM AUTHOR]

Photonic integrated circuits (PIC) devices are impacted by fabrication tolerances and therefore, prior knowledge of such variations could improve the PIC fabrication process and overall yield. This paper presents a method for predicting the fabrication impacts on a telecommunication optical digital to analog converter (oDAC)-based pulse amplitude modulator level four (PAM-4) transmitter as a case study where the certainty of this passive device is subjected to random variation. Our findings allow us to estimate the production yield in a fabrication scenario using the symbol error rate (SER) benchmark and this contributes to the study of the viability of oDAC PAM-4 transmitters to replace conventional electrical digital to analog converter (eDAC) PAM-4 transmitters. [ABSTRACT FROM AUTHOR]

This paper presents an energy‐efficient digital‐to‐analog converter (DAC) switching method with low common‐mode variations for high‐resolution successive approximation register (SAR) analog‐to‐digital converters (ADCs), while enabling to implement resolutions such as 14‐bit as compared to the typical 10‐bit. The proposed switching method enables high resolution by having a nearly constant common‐mode voltage and employing input‐swapping to use the reference voltage (Vref) only in the sampling phase. This method eliminates the need for the third reference voltage during the entire DAC switching steps, which reduces the required number of switches at the bottom plates of the capacitors. The use of lower number of switches not only lowers the DAC control logic complexity, but also results in a faster operation, lower power, and smaller area. When compared to conventional 10‐bit SAR ADCs, the proposed switching method in a 10‐bit implementation reduces the average energy and area by 96.09% and 75%, respectively, while offering high‐resolution implementation options such as 14 bits. [ABSTRACT FROM AUTHOR]

Due to nonideal residue amplification, the limited resolution of pipelined analog-to-digital converters (ADCs) has become a popular research topic for ADC designers. High-gain and high-speed amplifiers usually consume too much power for a decent ADC. Hence, this paper proposes a fast and cost-effective foreground calibration strategy for cyclic-pipelined ADCs. The calibration strategy compensates for the gain error due to inter-stage residual amplification, which alleviates the DC gain requirement for internal amplifiers. Unlike other digital calibrations, the proposed scheme is implemented with a cyclic-pipelined structure, and only one parameter needs to be calibrated, whose value can be feasibly calculated by the Fix-Point Iteration algorithm. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 6-bit sub-ADC four times with 1-bit redundancy each time. The calibration algorithm manages to recover the sampled data to 93.85 dB spurious free dynamic range (SFDR) even with a 57.8 dB-DC-gain amplifier. The total power consumption of ADC is 17.92 mW and it occupies an active area of 1.8 mm2. [ABSTRACT FROM AUTHOR]

Rapid advancements in micro-machining and microelectronics over the last few years have accelerated the growth of implanted medical devices that greatly improve a person's life. These devices first gather the signals from different nodes in/on the body, and then, they condition, multiplex, and digitize the signals. Thus, an analog-to-digital converter (ADC), which must continuously convert a variety of analog electrophysiological signals to digital codes, is one of the most crucial and power-hungry components. For implantable medical devices, the successive approximation register (SAR) ADC is a good choice. In this paper, a low-power single-ended SAR ADC architecture is proposed to offer good compromises between power efficiency, conversion accuracy, and design complexity. The proposed architecture supports 8-bit resolution at a sampling rate of 1 MS/s. Using a 130-nm CMOS process with 1.2 V supply voltage, an effective number of bits (ENOB) of 7.3 dB is achieved while 28.5 μW power is consumed. The ADC core only occupies an active area of about 197 μm × 377 μm. [ABSTRACT FROM AUTHOR]

This paper presents a modular hardware control system tailored for industrial applications. The system presented is designed with electrical protection, guaranteeing the reliable operation of its modules in the presence of various field noises and external disturbances. The modular architecture comprises a principal module (mP) and dedicated expansion modules (mEXs). The principal module serves as the network administrator and facilitates interaction with production and control processes. The mEXs are equipped with sensors, conditioning circuits, analog-to-digital converters, and digital signal processing capabilities. The mEX's primary function is to acquire local processing field signals and ensure their reliable transmission to the mP. Two specific mEXs were developed for industrial environments: an electrical signal expansion module (mSE) and the vibration signals expansion module (mSV). The EtherCAT protocol serves as a means of communication between the modules, fostering deterministic and real-time interactions while also simplifying the integration and replacement of modules within the modular architecture. The proposed system incorporates local and distributed processing in which data acquisition, processing, and data analysis are carried out closer to where data are generated. Locally processing the acquired data close to the production in the mEX increases the mP availability and network reliability. For the local processing, feature extraction algorithms were developed on the mEX based on a Fast Fourier Transform (FFT) algorithm and a curve-fitting algorithm that accurately represents a given FFT curve by significantly reducing the amount of data that needs to be transmitted over the mP. The proposed system offers a promising solution to use computational intelligence methodologies and meet the growing need for a modular industrial control system with reliable local data processing to reach a smart industry. The case study of acquiring and processing vibration signals from a real cement ball mill showed a good capacity for processing data and reducing the amount of data. [ABSTRACT FROM AUTHOR]

The anti-electromagnetic interference capability of partial discharge (PD) acoustic signal conversion and collection circuits severely restrict the sensitivity of PD detection. The data acquisition (DAQ) systems available in the current market are costly and have limited functionality, making it difficult to satisfy the acquisition requirements for PD detection. This paper proposes a medium to high-speed fiber optic signal acquisition board with an adjustably controlled sampling rate and filter cutoff frequency. The circuit achieves a higher signal-to-noise (SNR) ratio by distributing the noise in each part of the signal acquisition chain reasonably. The temperature characteristics of the acquisition module are improved by utilizing the programmable T-type structure for transimpedance amplification of photocurrent. The DAQ card performs data acquisition and processing using STM32H743 internal ADC and caches data in bulk with an SRAM and SD card. A data uploading method based on time reference has been proposed, which enables full, effective information signal upload through a low-cost transmission interface. The research ultimately achieves a stable sampling of three channels at 1 MSps, SNR of 63 dB, and programmable gain amplification of the photocurrent with 0–60 dB. Finally, the system is used for PD acoustic signal acquisition in the frequency range of 20 Hz to 100 kHz. [ABSTRACT FROM AUTHOR]

This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of −0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital). [ABSTRACT FROM AUTHOR]

High-resolution multi-channel digitizers are used extensively for precision low voltage measurements in numerous applications and allow the simultaneous measurement of voltage magnitude ratio and phase difference between two different waveforms in power system applications. Delta–sigma-based analog-to-digital conversion enables the use of sampling frequencies in the range of megahertz, which provides accurate measurement bandwidths for transformed high-frequency, high-voltage signals. With the increased use of power electronic converters contributing to high-frequency harmonic emissions in power systems, there is a growing interest in developing calibration systems to measure voltage ratio and phase difference of distorted fundamental frequency waveforms consisting of superimposed, high-frequency harmonics. However, information regarding the accuracy of the high-resolution digitizers in the measurement of distorted voltage waveforms is limited as characterization is typically performed under sinusoidal voltage waveform conditions. This paper presents the details of the accuracy characterization of a 24-bit resolution digitizer under both sinusoidal and distorted waveform conditions for measuring complex voltage ratio and phase error for frequencies up to 10 kHz. The detailed experimental results and the measurement uncertainty evaluations show that increased voltage ratio and phase difference errors should be allocated when these high-resolution digitizers are used to measure distorted voltage waveforms. The estimated expanded uncertainties of complex voltage ratio measurement and phase error measurement for harmonic frequencies up to 10 kHz are ±260 ppm and ±100 µrad, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables an aggressive noise transfer function while minimizing the power consumption associated with the use of an active filter. In the proposed ADC, the residue is generated by a capacitive digital-to-analog converter (CDAC) employing DWA, which is made possible by employing a second CDAC, which operates after the SAR operation is completed. The proposed ADC is designed with a 28 nm CMOS process with 1 V power supply. The simulation results show that the ADC achieves the SNDR of 71.2 dB and power consumption of 228 μW when operated with a sampling rate of 80 MS/s and oversampling ratio (OSR) of 10. The Schreier figure-of-merit (FoM) is 173.6 dB, and Walden FoM is 9.6 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support VCM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s. [ABSTRACT FROM AUTHOR]

In this paper, a temperature measurement system with NTC (Negative Temperature Coefficient) thermistors was designed. An MCU (Micro Control Unit) primarily operates by converting the voltage value collected by an ADC (Analog-to-Digital Converter) into the resistance value. The temperature value is then calculated, and a DAC (Digital-to-Analog Converter) outputs a current of 4 to 20 mA that is linearly related to the temperature value. The nonlinear characteristics of NTC thermistors pose a challenging problem. The nonlinear characteristics of NTC thermistors were to a great extent solved by using a resistance ratio model. The high precision of the NTC thermistor is obtained by fitting it with the Hoge equation. The results of actual measurements suggest that each module works properly, and the temperature measurement accuracy of 0.067 °C in the range from −40 °C to 120 °C has been achieved. The uncertainty of the output current is analyzed and calculated with the uncertainty of 0.0014 mA. This type of system has broad potential applications in industry fields such as the petrochemical industry. [ABSTRACT FROM AUTHOR]

A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 μ m CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply. [ABSTRACT FROM AUTHOR]

This paper introduces a single-slope analog-to-digital converter (SS ADC) with an embedded digital baseline calibration scheme designed to improve the accuracy and reliability of gas sensor measurements. The proposed SS ADC effectively leverages an up/down counter mechanism to ensure stable signal extraction from gas sensors, despite variations in the baseline distribution. The proposed SS ADC initiates with a down counting operation to capture the initial output value of the gas sensor, which, after A/D conversion, is stored as a reference point for future readings. Subsequent gas sensor output values are derived by performing an up counting operation from this baseline reference. This approach allows for real-time correction of the baseline during the SS A/D conversion process, obviating the need for complex post-processing and baseline correction algorithms. The proposed SS ADC with the baseline calibration scheme was designed using a 0.18 μm standard CMOS process to confirm its feasibility. It demonstrated a signal-to-noise and distortion ratio (SNDR) of 57.56 dB and a spurious-free dynamic range (SFDR) of 59.02 dB, resulting in an effective number of bits (ENOB) of 9.27 bits in the post-simulation level. The proposed SS ADC has a total power consumption of 1.649 mW. This work offers an efficient solution to the baseline distribution problem in gas sensors, facilitating more reliable and accurate gas detection systems. [ABSTRACT FROM AUTHOR]

This paper presents an AC-coupled, incremental analog-to-digital converter (ADC) based on two-step quantization for high-density implantable neural recording. It achieves a rail-to-rail electrode DC offset (EDO) rejection, low noise, a small area, and low power consumption. Fabricated in a 180 nm CMOS process, the prototype ADC achieves a high input impedance, 24 mVpp linear input range, and 58.9 dB signal-to-noise and distortion ratio (SNDR). Its core circuit has a power consumption of 12 μW and an area of 0.0192 mm2. The referred-to-input (RTI) noise is 6.9 μVrms within the bandwidth of 1 Hz–10 kHz. [ABSTRACT FROM AUTHOR]

In this paper, a wireless potentiostat code-named ElectroSense, for interfacing of wearable electrochemical biosensors, will be presented. The system is devoted to non-invasive monitoring of glucose in wearable medical applications. Differently from other potentiostats in literature, which use digital-to-analog converters (DACs) as discrete components or integrated in high-end microcontrollers, in this work the pulse width modulation (PWM) technique is exploited through PWM-DAC approach to generate signals. The ubiquitous presence of integrated PWM peripherals in low-end microcontrollers, which generally also integrate analog-to-digital converters (ADCs), enables both the generation and acquisition of read-out signals on a single cheap electronic device without additional hardware. By this way, system's production costs, power consumption, and system's size are greatly reduced with respect to other solutions. All these features allow the system's adoption in wearable healthcare Internet-of-things (IoT) ecosystems. A description of both the sensing technology and the circuit will be discussed in detail, emphasizing advantages and drawbacks of the PWM-DAC approach. Experimental measurements will prove the efficacy of the proposed electronic system for non-invasive monitoring of glucose in wearable medical applications. [ABSTRACT FROM AUTHOR]

This paper presents a level-crossing successive-approximation-register (LC-SAR) hybrid analog-to-digital converter (ADC) that combines an LC ADC with an SAR ADC, which may be used for Internet of Things (IoT) random sparse event scenarios. The sampling frequency of a traditional LC ADC is usually proportional to the maximum instantaneous rate of change of the input signal; therefore, a higher input signal frequency inevitably leads to higher system power consumption. However, the proposed hybrid ADC uses the input level difference between the two moments before and after level-crossing detection, thereby ensuring a higher conversion precision and lower power consumption, even at higher input signal frequencies. Compared with traditional LC ADC or SAR ADC, the proposed hybrid ADC combines the ultralow-power advantage of LC ADC with the high-precision advantage of SAR ADC in converting IoT data with sparse characteristics such as ECG, EEG, and brain potential. The LC-SAR hybrid ADC is designed with a 0.18 μm CMOS process and consumes 4.34 μW at a 1.8 V supply voltage, achieving an SNDR of 67.41 dB and a bandwidth of 20 kHz. The spectrum analysis result was 10.85 ENOB when the input sinusoidal signal was 14.975 kHz. When inputted with an ECG signal, the system power consumption was as low as 0.49 μW. Furthermore, the proposed hybrid ADC obtained a good figure of merit, with FoMw and FoMs reaching 58.8 fJ/conv.steps and 164 dB, respectively. Compared to a conventional uniform sampling ADC, approximately 80% of the power savings and an 8x compression ratio can be achieved in physiological signal acquisition applications. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to the reconfigurable digital down converter (DDC) reducing the sampling frequency from 3.64 GHz to 28.4375 MHz on the field-programmable gate array (FPGA) device. The proposed DDC consists of a polyphase mixer and a resampling filter. The polyphase mixer can reduce the high-speed sampling rate signal and generates a complex baseband signal having sufficient noise margin. The resampling filter produces a large decimation factor and improves the filtering quality. The design has been optimized at the sub-component level using very few multiplier blocks, resulting in low power consumption. The sampling rate factors can be dynamically programmed in real-time to increase the flexibility of the design. In addition, truncation is used in each filter stage to protect from overflow errors. Moreover, the design is described in optimum hardware description language to reduce the available resources, without compromising the functionality. Finally, the proposed DDC has been simulated and tested on the Xilinx Kintex-7 FPGA board. According to synthesis results, it is noticed that the proposed design reduces the area and power consumption compared to other existing architectures. In the end, the feasibility of the proposed architecture is tested to certify the system's validity. [ABSTRACT FROM AUTHOR]

The majority of data exchanged between connected devices are confidential and must be protected against unauthorized access. To ensure data protection, so-called cryptographic algorithms are used. These algorithms have proven to be mathematically secure against brute force due to the key length, but their physical implementations are vulnerable against physical attacks. The physical implementation of these algorithms can result in the disclosure of information that can be used to access confidential data. Some of the most powerful hardware attacks presented in the literature are called fault injection attacks. These attacks involve introducing a malfunction into the normal operation of the device and then analyzing the data obtained by comparing them with the expected behavior. Some of the most common methods for injecting faults are the variation of the supply voltage and temperature or the injection of electromagnetic pulses. In this paper, a hardware design methodology using analog-to-digital converters (ADCs) is presented to detect attacks on cryptocircuits and prevent information leakage during fault injection attacks. To assess the effectiveness of the proposed design approach, FPGA-based ADC modules were designed that detect changes in temperature and supply voltage. Two setups were implemented to test the scheme against voltage and temperature variations and injections of electromagnetic pulses. The results obtained demonstrate that, in 100% of the cases, when the correct operating voltage and temperature range were established, the detectors could activate an alarm signal when the cryptographic module was attacked, thus avoiding confidential information leakage and protecting data from being exploited. [ABSTRACT FROM AUTHOR]

This paper presents a novel dynamic bias latch‐type comparator combined with a voltage‐controlled delay line (VCDL), designed specifically for low‐power and low‐noise applications in high‐speed analog‐to‐digital converters (ADCs). The incorporation of the VCDL precedes the dynamic bias amplifier in the proposed comparator, thereby achieving a balance between energy efficiency and high‐speed operation. This innovative design enhances the input common voltage of the dynamic bias amplifier through the utilization of the VCDL, surpassing that of a conventional dynamic bias comparator. Furthermore, it demonstrates increased adaptability in technology scaling and efficient operation at lower supply voltages, leveraging inverters and other simple cells. The proposed comparator in 28 nm process technology achieves a 309.7 µV input‐referred noise while consuming approximately 145.8 fJ and completing comparisons in 125 ps with a 0.9 V supply and a 0.45 V input common‐mode voltage. [ABSTRACT FROM AUTHOR]

The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as C n = 2 × C n − 1 , the variable capacitor C n of ADC1 can be updated to be closest to the sum of C n − 1 of ADC1 and C n − 1 of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the C n of ADC1 can be connected with two of the C n − 1 of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update C n . This process is iterated, until C n is in agreement with the sum of two of C n − 1 . Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by 21.8 dB and 6.4 dB, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable hybrid Analog to Digital Converter (ADC) designed specifically for bio-signal processing, aiming to achieve low power consumption and high area efficiency. The proposed ADC utilizes a combination of 10-bit Most Significant Bit (MSB) Successive Approximation Register (SAR) and 2–4-bit Least Significant Bit (LSB) Single Slope (SS) architectures. The SS architecture incorporates the Dummy Capacitor Quantization Method (DCQM) which employs a 10-bit MSB dummy capacitor. This dummy capacitor can be configured to represent the 2-LSBs or reconstruct 4-LSBs. The reconfigurability of the ADC is achieved through the control of the reset timing of a 5-bit counter enabled by an external signal. The proposed ADC was fabricated using a Complementary Metal Oxide Semiconductor (CMOS) n-well 1-poly 8-metal process. Experimental measurements revealed that the ADC operates at a speed of 454 kS/s with power consumption of 18.7 μW. The Effective Number of Bits (ENoB) achieved by the ADC is 10.9 bits based on a 14-bit scale or 10.2 bits based on a 12-bit scale. The Figure of Merit (FoM) for the ADC is calculated to be 21.5 fJ/step for the 14-bit scale and 22.1 fJ/step for the 12-bit scale. [ABSTRACT FROM AUTHOR]

This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 Vpp, with a SNDR of 80.45 dB, ENOB of 13.07, SFDR of 87.16 dB and dissipates an average power of 0.8 mW, while operating at 2.5 V/1 V for analog/digital power supply. The INL and DNL is +0.22/−0.34 LSB and +0.42/−0.3 LSB, respectively. A prototype ADC has been fabricated in a conventional CMOS 65 nm technology process. [ABSTRACT FROM AUTHOR]

Portable sensor systems are usually based on microcontrollers and/or Field-Programmable Gate Arrays (FPGAs) that are interfaced with sensors by means of an Analog-to-Digital converter (ADC), either integrated in the computing device or external. An alternative solution is based on the direct connection of the sensors to the digital input port of the microcontroller or FPGA. This solution is particularly interesting in the case of devices not integrating an internal ADC or featuring a small number of ADC channels. In this paper, a technique is presented to directly interface sensors with analog voltage output to the digital input port of a microcontroller or FPGA. The proposed method requires only a few passive components and is based on the measurements of the duty cycle of a digital square-wave signal. This technique was investigated by means of circuit simulations using LTSpice and was implemented in a commercial low-cost FPGA device (Gowin GW1NR-9). The duty cycle of the square-wave signal features a good linear correlation with the analog voltage to be measured. Thus, a look-up table to map the analog voltage values to the measured duty cycle is not required with benefits in terms of memory occupation. The experimental results on the FPGA device have shown that the analog voltage can be measured with a maximum accuracy of 1.09 mV and a sampling rate of 9.75 Hz. The sampling rate can be increased to 31.35 Hz and 128.31 Hz with an accuracy of 1.61 mV and 2.68 mV, respectively. [ABSTRACT FROM AUTHOR]

The noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is an innovative hybrid structure that offers performance advantages. The NS-SAR ADC leverages the SAR ADC as its foundation and combines oversampling technology and noise-shaping technology found in Sigma-Delta ADC. This integration effectively combines the strengths of both structures and enhances overall performance. The ADC features a simple circuit structure, compact chip area, and high energy efficiency, which has positioned it as a prominent research area. In this paper, leveraging the TSMC 65 nm GP process, the NS-SAR ADC is designed with a power supply voltage of 1 V. This design adopts an 8-bit differential capacitor structure, operates at a sampling frequency of 16 MS/s, and achieves an oversampling rate of 16 times the desired performance indicators. Through extensive circuit post simulation verification, the SNR obtained reaches 78 dB, providing an effective bit resolution of 12.7 bits. The core chip area of the ADC measures 366 × 333 μm2, while the power consumption is impressively low at 417 μW and FoMs is 168 dB. [ABSTRACT FROM AUTHOR]

The simultaneous transmit and receive (STAR) array system provides higher radiation gain and data rate compared to traditional radio system. Because of the various mutual couplings between each pair of transmit and receive elements, it is a great challenge to suppress the incident self-interference power at multiple receive elements, which is usually much higher than the desired signal of interest (SoI) power and causes the saturation of receive links and the distortion of the digital SoI. In this paper, we propose an optimized method for transmit beamforming based on radiation power constraints and transmit power control. Through adaptive transmit beamforming, high isolation between the transmit array and each receive link is achieved, minimizing the self-interference power at each receiving element. This method effectively reduces the self-interference power, avoiding distortion of the SoI digital signal caused by limited-bit analog-to-digital converters (ADCs). Simulation results demonstrate that this optimized transmit beamforming method can achieve more than 100 dB effective isotropic isolation (EII) on a 32-element two-dimensional phased array designed in HFSS, reducing the maximum incident self-interference power at the receive channels by approximately 35 dB, while effectively controlling the attenuation of the transmit gain. We also present the advantages in receive subarray isolation and lower ADCs digits under the transmit ABF method. [ABSTRACT FROM AUTHOR]

This paper proposes a non-contact current measurement method for three-phase rectangular busbars based on TMR (tunneling magneto-resistance) sensors, due to their advantages of large dynamic range, wide bandwidth, light weight, and easy installation. A non-contact current sensor composed of only three TMR sensors is developed and the TMR sensors are respectively placed at a location with a certain distance from the surface of each rectangular busbar to measure the magnetic fields generated by the busbar currents. To calibrate the developed current sensor, i.e., to establish the relationship between the magnetic fields measured by the TMR sensors and the currents flowing in the three-phase rectangular busbars, we designed a thyristor-controlled resistive load as a calibrator, which is connected to a downstream branch of the distribution cabinet. By switching the resistive load, a calibration current, which can be identified from the background current, is generated in one rectangular busbar and its value is measured at the location of the calibrator, and transmitted wirelessly to the location of the TMR sensors. A new and robust method is proposed to extract the voltage components, corresponding to the calibration current, from the voltage waveforms of the TMR sensors. By calculating the proportional coefficients between the calibration currents and the extracted voltage components, online calibration of the current sensor is achieved. We designed and implemented a current measurement system consisting of a current sensor using TMR sensors, a thyristor-controlled resistive load for current sensor calibration, and a data acquisition circuit based on a multi-channel analog-to-digital converter (ADC). Current measurement experiments were performed in a practical distribution cabinet installed in our laboratory. Compared to the measurement results using a commercial current probe with an accuracy of 1%, the relative error of the measured currents in RMS is less than 2.5% and the phase error is less than 1°, while the nonlinearity error of the current sensor is better than 0.8%. [ABSTRACT FROM AUTHOR]

A totem-pole bridgeless boost converter is one of the most promising topologies for the power factor correction (PFC) stage in high-power applications due to its high efficiency and small number of components. However, due to the totem-pole structure of the field-effect transistor (FET), very high switching loss occurs via the reverse recovery current of the body diode. To solve these problems, critical mode (CRM) control is a good solution to achieve the valley switching technique. With valley switching of CRM control, the switching loss decreases drastically with decreasing turn-on voltage. But, although the CRM control enables valley switching, it is hard to make an exact valley switching control with general zero-voltage detection circuits. In addition, when a frequency limitation scheme is applied to prevent a very high frequency, the switch can operate with hard switching at the boundary of the frequency limitation. Furthermore, the CRM boost PFC has a low PF and high total harmonic distortion (THD) under light-load conditions due to the large negative current resulting from resonance between the inductor and parasitic capacitance. It becomes worse at near-zero input voltage since the resonance current becomes larger near zero-input voltage. Therefore, in this paper, a totem-pole bridgeless boost PFC converter with high efficiency, high PF, and low THD is developed using TMS320F28377 by Texas Instruments. Based on the basic digital structure of the totem-pole bridgeless converter, the proposed controls help with exact valley switching, PF and THD improvement, and frequency limitation. The prototype converter is verified using 90–264 VAC input voltages and 450 V/3.3 kW output specifications. [ABSTRACT FROM AUTHOR]

This paper presents a new successive approximation register (SAR)-assisted pipeline analog-to-digital converter (ADC). The coarse stage digital-to-analog converter (DAC) of the proposed ADC is divided into three separate capacitor arrays (a small-DAC and two big-DACs) to increase the sampling rate while simultaneously reducing the power consumption. The small-DAC performs the low-power coarse conversion, and the two big-DACs generate low-noise residue voltage in a ping-pong configuration, reducing the power consumption of the residue amplification. The big-DACs are not involved in the coarse conversion. So, any mismatch between them does not significantly degrade the overall linearity. The unit capacitors of the CDACs are determined according to a comprehensive analysis, including the overall input-referred noise, the bandwidth mismatch, and the static nonlinearity associated with the ping-pong configuration. The proposed ADC is designed and simulated in a 65 nm CMOS technology over process variations. At 1.2 V supply, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 56.1 dB and a spurious-free dynamic range (SFDR) of 67.3 dB for a Nyquist frequency input sampled at 100 MS/s. The total power consumption is 2.28 mW, resulting in a Walden figure of merit (FoM) of 43 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an "on-the-ramp processing" technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW. [ABSTRACT FROM AUTHOR]

This paper introduces a low-power fully differential fixed window level-crossing analog-to-digital converter (LC-ADC) for wireless medical implantable devices. The LC-ADC could be an excellent candidate for low-power systems due to the reduction of sampling points for bio-potential signals. Different from existing fixed window LC-ADCs, which use a 1-bit DAC or scaler and two reference levels to move the input signal to the comparison window, a simplified scheme is proposed in which the DAC or scaler is removed and a single-reference level is used to create the comparison window. The proposed LC-ADC utilizes a single-reference comparator, which leads to a simplified implementation and significant reduction in power consumption and circuit area. In addition, using a single reference level and removing DAC, leads to a decrease in the complexity of the controlling logic. The proposed LC-ADC is simulated in 0.18 μ m CMOS technology. The simulation results achieve an effective number of bits (ENOB) of up to 6.5 bits with about 59–141 nW power consumption under 0.8 V supply and input signal bandwidth from 5 Hz to 4 kHz. [ABSTRACT FROM AUTHOR]

This paper presents a high-resolution 18-bit SAR ADC with a high 10-bit capacitor DAC and a low 8-bit resistor DAC. The total required number of the unit capacitors is decreased to 512. Foreground digital calibration based on capacitive recombination is introduced to improve linearity. Preamplifiers and output offset storage(OOS) enhance the noise and offset performance of the comparator. As a result, the design under 180 nm process achieves a signal-to-noise and distortion ratio(SNDR) of 105.5dB and a spurious-free dynamic range (SFDR) of 116.3dB under 1 MS/s sampling rate with a single channel. The effective number of bits (ENOB) can reach 17.23 bits with a Nyquist-rate input while consuming 46 mW from a 5 V supply. The resultant Schreier and Walden figures of merit (FoM) are 178.92 dB and 295.34 fJ/conversion-step, respectively. The proposed SAR ADC occupies an actual area of 3850 μ m by 2810 μ m. [ABSTRACT FROM AUTHOR]

This paper introduces a novel algorithm for optimizing the coefficients of the digital filters used in incremental delta-sigma analog-to-digital converters (IDSC). This algorithm is modified from constrained linear least squares (LS) to improve the signal-to-noise-and-distortion ratio (SNDR) of IDSC and minimize the oversampling rate (OSR) of the modulator, which enhances system speed and reduces power consumption. In the case of the same SNDR, the first-order IDSC with the proposed filter can reduce the OSR of the modulator by 50%, at least compared to the IDSC with the conventional filter. The second-order IDSC with the proposed filter can reach a higher SNDR of 106 dB with an OSR of 64. Considering the nonlinearity of the integrator, the SNDR of IDSC with the proposed filter is also 10 dB greater than that of the conventional filters and 3dB greater than that of the IDSC using the near-optimal algorithm filter. The experimental results indicate that the proposed filter possesses an excellent figure of merit of 0.028 pJ / conv . [ABSTRACT FROM AUTHOR]

This paper presents a novel jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is helpful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL) and time-based circuits whose performance is severely degraded by high jitter. In the proposed technique, the jitter is extracted using Excess Phase Discrimination (EPD) block and is transformed into Pulse Width Modulated (PWM) signal, which is then fed into the Phase Compensator (PC) block. This block reduces the jitter by about half its value after enabling the Single Ended Injection Locking (SEIL). The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. On enabling the proposed circuit, the Root Mean Square (RMS) jitter reduces from 5.94 to 2.58 ps (about 56%) for VCRO running at 58 MHz and consumes a total power of 375.84 μ W. The overall performance of the proposed circuit does not vary much in the post-layout simulations, hence demonstrating the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

The integration of multiterminal hybrid HVDC grids connecting LCC- and VSC-based networks faces several technical challenges such as DC fault isolation, ensuring multi-vendor interoperability, managing high DC voltage levels, and facilitating high-speed power reversal without interruptions. The two-stage DC-DC converter emerges as a key solution to address these challenges. By implementing the modular multilevel converter (MMC) structure, the converter's basic topology includes half-bridge sub-modules on the VSC side and full-bridge sub-modules on the LCC side. However, while this topology has been discussed in the literature, its connection to an LCC-based network with controlled current magnitude lacks detailed analysis regarding operational challenges, control strategies under various scenarios, and design considerations. This paper fills this gap by providing comprehensive mathematical analysis, design insights, and control strategies for the modular DC-DC converter to regulate DC voltage on the LCC-HVDC side. Additionally, the proposed control scheme minimizes the interfacing inductor between the two bridges, ensuring uninterrupted power flow during reversal and effective handling of DC faults. Validation through Control-Hardware-in-the-Loop testing across diverse operational and fault scenarios, along with a comparative analysis of different converters, further strengthens the findings. © 2017 Elsevier Inc. All rights reserved. [ABSTRACT FROM AUTHOR]

This paper presents a least-mean-square-based (LMS-based) background calibration algorithm with reinforcement learning optimization to calibrate the capacitor mismatch in successive approximation-register (SAR) analog-to-digital converters (ADCs). When calibrating capacitor mismatch, the convergence speed and stability of the conventional LMS-based algorithm cannot be balanced due to the fixed iteration step size. To improve the calibration effect, nine different iteration step sizes are proposed for calibration. An iteration step size selection strategy is obtained by training the Q-learning algorithm with the conventional LMS-based calibration iteration process. Leading by this strategy, the proposed calibration algorithm performs better convergence speed and stability than the conventional LMS-based calibration algorithm. A 12-bit sub-radix-2 redundant SAR ADC is used to test our proposed calibration algorithm for better evaluation. Behavioral simulations show that the proposed calibration algorithm converges at 0.065 M sampling points, and the standard deviation of the effective number of bits (ENOB) in the convergence state is only 0.034-bit. [ABSTRACT FROM AUTHOR]

As a sub-Nyquist sampling structure based on compressed sensing (CS), modulated wideband converter (MWC) was proposed to overcome the sampling rate limitation of analog-to-digital converters (ADCs) for wide spectral multiband signals. Different from ideal conditions when analyzing its theory, in practice, the MWC system is implemented with non-ideal devices. Due to this deviation between the ideal model and practical hardware, any imperfection of the analog device will lead to an imperfect signal reconstruction. Although the non-ideal factors can be compensated and calibrated, the conventional compensation and calibration methods easily introduce additional phase errors. This paper aims to evaluate the impact of those phase errors on signal reconstruction performance. We point out that phase errors deteriorate the normalized mean squared errors (NMSE) and even lead to incorrect support set recovery in serious cases. We thus propose a method using the SINC signal and DC signal to measure the MWC channel response which avoids the phase errors introduced in the compensation process. To verify this method, an MWC system and a measuring platform are implemented on hardware. The measurement results show that the recovery NMSE of − 13.09dB is achieved after being measured and compensated with an input SNR of 25.47dB. [ABSTRACT FROM AUTHOR]

This paper proposes a 500 MS/s 4-bit flash analog-to-digital converter (ADC) featuring a differential input voltage range of 1.2 Vpp operating at a supply voltage of 1.2 V. Although the proposed circuit utilizes a conventional flash ADC structure, its track and hold circuit, driving buffer, and preamp circuits corresponding to the analog stages are designed using complementary architecture to attain a sufficient swing range even at a low supply voltage. Notably, the proposed structure satisfies the error requirements. The error source of the flash ADC, such as the comparator's input referred offset, did not degrade its performance, while the use of a calibration circuit, characterized by power consumption and area burdens and increased complexity, could also be avoided. Therefore, the proposed flash ADC met the error requirements, such as the comparator's input referred offset, without the need for calibration circuits. The chip, fabricated using the TSMC 65 nm process, covers an area of 1,160 × 950 μm² and consumes 78 mW of power. Furthermore, its signal-to-noise and distortion ratio and spurious-free dynamic range were measured to be 23.36 dB and 30.26 dB, respectively, at a sampling frequency of 500 MHz. [ABSTRACT FROM AUTHOR]