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In this paper, the electrothermal coupling model of metal oxide resistive random access memory (RRAM) is analyzed by using a 2D axisymmetrical structure in COMSOL Multiphysics simulation software. The RRAM structure is a Ti/HfO2/ZrO2/Pt bilayer structure, and the SET and RESET processes of Ti/HfO2/ZrO2/Pt are verified and analyzed. It is found that the width and thickness of CF1 (the conductive filament of the HfO2 layer), CF2 (the conductive filament of the ZrO2 layer), and resistive dielectric layers affect the electrical performance of the device. Under the condition of the width ratio of conductive filament to transition layer (6:14) and the thickness ratio of HfO2 to ZrO2 (7.5:7.5), Ti/HfO2/ZrO2/Pt has stable high and low resistance states. On this basis, the comparison of three commonly used RRAM metal top electrode materials (Ti, Pt, and Al) shows that the resistance switching ratio of the Ti electrode is the highest at about 11.67. Finally, combining the optimal conductive filament size and the optimal top electrode material, the I-V hysteresis loop was obtained, and the switching ratio Roff/Ron = 10.46 was calculated. Therefore, in this paper, a perfect RRAM model is established, the resistance mechanism is explained and analyzed, and the optimal geometrical size and electrode material for the hysteresis characteristics of the Ti/HfO2/ZrO2/Pt structure are found. [ABSTRACT FROM AUTHOR]

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A "sandwich" capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays' benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages. [ABSTRACT FROM AUTHOR]

Artificial neural network‐based computing is anticipated to surpass the von Neumann bottleneck of traditional computers, thus dramatically boosting computational efficiency and showing a wide range of promising applications. In this paper, sol−gel deposition was used to prepare thin films of samarium‐doped hafnium dioxide (Sm:HfO2). When Sm is doped at a concentration of 4%, it mimics biological synapses; meantime, by voltage scanning, an obvious mimicry of resistive switching can be detected, demonstrating that the technology may be applied to simulate biological synapse characteristics, including long‐term potentiation (depression), short‐term potentiation (depression), paired‐pulse facilitation, and learning rules of spike‐time‐dependent plasticity. Additionally, a pulsed neural network is built on the MNIST dataset to test the memristor's capacity to handle visual input. The findings show the possibility of synthetic synapses in artificial intelligence systems that integrate neuromorphic computing with synaptic brain activity. [ABSTRACT FROM AUTHOR]

Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry's introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM) is a promising technology for AI Processing-in-Memory (PIM) hardware because of its compatibility with CMOS, small footprint, and ability to complete matrix–vector multiplication workloads inside the memory device itself. However, redundant computations are brought on by duplicate weights and inputs when an MVM has to be split into smaller-granularity sequential sub-works in the real world. Recent studies have proposed repetition-pruning to address this issue, but the buffer allocation strategy for enhancing buffer device utilization remains understudied. In preliminary experiments observing input patterns of neural layers with different datasets, the similarity of repetition allows us to transfer the buffer allocation strategy obtained from a small dataset to the computation with a large dataset. Hence, this paper proposes a practical compute-reuse mechanism for ReRAM-based PIM, called CRPIM, which replaces repetitive computations with buffering and reading. Moreover, the subsequent buffer allocation problem is resolved at both inter-layer and intra-layer levels. Our experimental results demonstrate that CRPIM significantly reduces ReRAM cells and execution time while maintaining adequate buffer and energy overhead. [ABSTRACT FROM AUTHOR]

In this work, a machine learning‐assisted prediction model is proposed to analyze the reliability issues in the 28 nm resistive random access memory (RRAM) chip with raw data measured from RRAM test chip. The neural network of long‐short time memory (LSTM) is trained by the voltages and resistance during the endurance test (input vectors) and generates the output of the dichotomy states with a satisfied testing result >83.08%. According to the prediction results, the "real fail" state or "fake fail" state of the devices can get in the future. By collaborating with a well‐designed resurrection algorithm (RA), the percentage of real and fake failed cells dropped by 35% and 29%, respectively. Besides, the tail bits in retention significantly reduced from 33% to 14.6% due to the reduction of oxygen vacancies in the gaps of conducting filaments by applying ten consecutive cycles of RA. This intelligent prediction and repair module can prolong the lifetime of RRAM chips effectively in practical applications. [ABSTRACT FROM AUTHOR]

To reach the energy efficiency and the computing capability of biological neural networks, novel hardware systems and paradigms are required where the information needs to be processed in both spatial and temporal domains. Resistive switching memory (RRAM) devices appear as key enablers for the implementation of large-scale neuromorphic computing systems with high energy efficiency and extended scalability. Demonstrating a full set of spatiotemporal primitives with RRAM-based circuits remains an open challenge. By taking inspiration from the neurobiological processes in the human auditory systems, we develop neuromorphic circuits for memristive tonotopic mapping via volatile RRAM devices. Based on a generalized stochastic device-level approach, we demonstrate the main features of signal processing of cochlea, namely logarithmic integration and tonotopic mapping of signals. We also show that our tonotopic classification is suitable for speech recognition. These results support memristive devices for physical processing of temporal signals, thus paving the way for energy efficient, high density neuromorphic systems. Processing spatiotemporal information calls for the construction of hardware systems with computing capability comparable to biological neural networks. Inspired by human cochlea, Milozzi et al. develop neuromorphic circuits for memristive tonotopic mapping via volatile resistive switching memory devices. [ABSTRACT FROM AUTHOR]

Neuromorphic computing has emerged as an alternative computing paradigm to address the increasing computing needs for data-intensive applications. In this context, resistive random access memory (RRAM) devices have garnered immense interest among the neuromorphic research community due to their capability to emulate intricate neuronal behaviors. RRAM devices excel in terms of their compact size, fast switching capabilities, high ON/OFF ratio, and low energy consumption, among other advantages. This review focuses on the multifaceted aspects of RRAM devices and their application to brain-inspired computing. The review begins with a brief overview of the essential biological concepts that inspire the development of bio-mimetic computing architectures. It then discusses the various types of resistive switching behaviors observed in RRAM devices and the detailed physical mechanisms underlying their operation. Next, a comprehensive discussion on the diverse material choices adapted in recent literature has been carried out, with special emphasis on the benchmark results from recent research literature. Further, the review provides a holistic analysis of the emerging trends in neuromorphic applications, highlighting the state-of-the-art results utilizing RRAM devices. Commercial chip-level applications are given special emphasis in identifying some of the salient research results. Finally, the current challenges and future outlook of RRAM-based devices for neuromorphic research have been summarized. Thus, this review provides valuable understanding along with critical insights and up-to-date information on the latest findings from the field of resistive switching devices towards brain-inspired computing. [ABSTRACT FROM AUTHOR]

A nonlinear system, exhibiting a unique asymptotic behaviour, while being continuously subject to a stimulus from a certain class, is said to suffer from fading memory. This interesting phenomenon was first uncovered in a non-volatile tantalum oxide-based memristor from Hewlett Packard Labs back in 2016 out of a deep numerical investigation of a predictive mathematical description, known as the Strachan model, later corroborated by experimental validation. It was then found out that fading memory is ubiquitous in non-volatile resistance switching memories. A nonlinear system may however also exhibit a local form of fading memory, in case, under an excitation from a given family, it may approach one of a number of distinct attractors, depending upon the initial condition. A recent bifurcation study of the Strachan model revealed how, under specific train stimuli, composed of two square pulses of opposite polarity per cycle, the simplest form of local fading memory affects the transient dynamics of the aforementioned Resistive Random Access Memory cell, which, would asymptotically act as a bistable oscillator. In this manuscript we propose an analytical methodology, based on the application of analysis tools from Nonlinear System Theory to the Strachan model, to craft the properties of a generalised pulse train stimulus in such a way to induce the emergence of complex local fading memory effects in the nano-device, which would consequently display an interesting tuneable multistable oscillatory response, around desired resistance states. The last part of the manuscript discusses a case study, shedding light on a potential application of the local history erase effects, induced in the device via pulse train stimulation, for compensating the unwanted yet unavoidable drifts in its resistance state under power off conditions. [ABSTRACT FROM AUTHOR]