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Due to ultrafast switching speed and high-frequency switching of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (mosfets), crosstalk effect, high turn-on losses and electromagnetic interference are becoming constraints to the efficient and safe applications of SiC mosfets. The split-output structure has attracted widespread attention due to its advantages of overcoming the above constraints by integrating decoupling inductors. Thereby, it fully exploits the potential benefits of SiC mosfets. In this article, the effects of the split inductors on short-circuit characteristics of split-output power module are analyzed. An analytical model of the split-output power module is established to compare the electrical characteristics of the split inductors under normal operation and short-circuit faults. A dedicated short-circuit protection method is proposed based on the detection of the voltage pulse duration across the split inductors. The protection method is validated by hard switching fault and fault under load experiments. The results show that the short-circuit power device can be shut down when the short-circuit current is much lower than the continuous drain current. Besides, the short-circuit energy of the power device has the same order of magnitude as the dissipated energy under normal switching, which avoids degradation and even destruction of SiC mosfets under short-circuit faults.

In this article, a multiport network approach is proposed to analyze the forced oscillations issue for the multichips power module. First, experimental results indicate the presence of multiple resonance points caused by forced oscillations during the switching process of multichip power modules. Due to the complex distribution of parasitic parameters within the module, it is challenging to establish an accurate analytical model. Therefore, this article proposes a method based on multisoftware collaborative simulation to extract the corresponding impedance of different chip ports. In addition, the impact of bus parasitic inductance and chip capacitances on port impedance is obtained. Compared with the experimental result, the error of dominant frequency obtained by the proposed model is less than 3%. Furthermore, the sensitivity of the spatial near-field spectrum to bus voltage and load current is studied based on experimental results. Finally, the suppression methods for forced oscillations are proposed based on the aforementioned theoretical analysis from the perspectives of both chips and packaging. The effectiveness of proposed methods is verified through experimental results.