Search

This work presents a general enhancement in operational transconductance amplifiers (OTAs) by conjugating the diode-connected topologies of the current mirrors (CMs). The proposed conjugation method provides an internal high-impedance node, by which the transconductance of the amplifier is significantly increased. Since the central node of the conjugated CMs is virtually grounded for small differential signals, the cascode devices of the diode-connected topologies can be employed as an extra differential pair causing a further enhancement in transconductance. Moreover, the large signal behavior of the circuit shows that the conjugated CMs are capable of copying a dynamic current with a higher gain in comparison with a traditional CM amplifier. This advantage results in faster charging and discharging of the output capacitive load, which provides a larger slew rate (SR) without increasing the quiescent current. The proposed amplifier was manufactured with TSMC 0.18- $\mu $ m CMOS technology occupying a silicon area of $55.5\times 48.9~\mu $ m. Experimental results at a supply voltage of 1.8 V show a gain bandwidth (GBW) of 104.9 MHz, a dc gain of 79.1 dB, and an SR of 55.7 V/ $\mu $ s for a capacitive load of 10 pF, while the circuit consumes 489- $\mu $ W power.

This paper presents a chopper-stabilized three-stage operational amplifier (OpAmp) with a unity gain bandwidth of 69 MHz and an input referred noise density of 3 nV $/\surd {Hz}$ . The proposed design achieves a stable unity gain by proposing a new pole and zero scheme with very low power consumption, drawing only 3.3 mA from a 1.8 V power supply while driving a load capacitor as large as 100pF. To achieve rail-to-rail input swing, the design uses both NMOS and PMOS differential pairs at the input and biases them in the subthreshold region to provide an identical net trans-conductance over the rail-to-rail input common mode. Furthermore, an adaptive biasing is employed and the current sources are kept ON during large signal transitions at the input, thus eliminating crossover distortion and providing a high slew rate of 40 V/ $\mu \text{s}$ at a 100 pF load capacitor. The design employs chopping at 2.5 MHz and is enhanced with a local ripple reduction loop, making the OpAmp suitable for high gain and wide bandwidth applications with less filtering required. The design also reduces the input bias current significantly from 500 nA to 1.5 nA by buffering the input and applying it to the modified bootstrap switches. The proposed OpAmp, fabricated in a $0.18~\mu \text{m}$ CMOS process, exhibits a maximum offset of $4.5~\mu \text{V}$ , a flicker noise corner frequency of 246 Hz, a DC gain of 146 dB, a power supply rejection ratio of 123 dB, and a common mode rejection ratio of 116 dB.