18 results on '"Cyu, Ruei-Hong"'
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2. Phase-engineered heterostructures of Mo2C by plasma-assisted selenization and sulfurization processes toward excellent hydrogen evolution reaction
3. Rational Design of Phase-Engineered WS2/WSe2 Heterostructures by Low-Temperature Plasma-Assisted Sulfurization and Selenization toward Enhanced HER Performance
4. Ultrathin α‑Bi2O3 Thin-Film Transistor for Cost-Effective Oxide-TFT Inverters.
5. Ultrathin α-Bi2O3Thin-Film Transistor for Cost-Effective Oxide-TFT Inverters
6. Rational Design of Phase-Engineered WS2/WSe2 Heterostructures by Low-Temperature Plasma-Assisted Sulfurization and Selenization toward Enhanced HER Performance.
7. Rational design of comb-like 1D–1D ZnO–ZnSe heterostructures toward their excellent performance in flexible photodetectors.
8. High‐Performance Monolithic 3D Integrated Complementary Inverters Based on Monolayer n‐MoS2 and p‐WSe2
9. Enhanced Electrical Transport Properties of Molybdenum Disulfide Field-Effect Transistors by Using Alkali Metal Fluorides as Dielectric Capping Layers.
10. High‐Performance Monolithic 3D Integrated Complementary Inverters Based on Monolayer n‐MoS2 and p‐WSe2.
11. Design of Mixed-Dimensional QDs/MoS2/TiO2 Heterostructured Resistive Random-Access Memory with Interfacial Analog Switching Characteristics for Potential Neuromorphic Computing.
12. Design of Versatile Top‐Down Transfer by Thermal Release Tape/Poly(methyl methacrylate) (TRT/PMMA) Bi‐Supporting Layers Toward All‐Transfer Transition Metal Dichalcogenide Material Based Transistor Arrays.
13. Controllable Oxygen‐Incorporated 2D‐SnSe2 Layered Thin Film by Plasma‐Assisted Selenization Process with Enhanced NO2 Gas Sensitivity and Improved Humidity Stability.
14. Rational Design of Phase-Engineered WS2/WSe2Heterostructures by Low-Temperature Plasma-Assisted Sulfurization and Selenization toward Enhanced HER Performance
15. Figure-of-Merit in 2D Insulators Pertaining to the Thermokinetics of Hexagonal Boron Nitride via Atmospheric-Pressure Chemical Vapor Deposition (APCVD) on Cu: Origin and Scenario
16. Ultrathin α-Bi 2 O 3 Thin-Film Transistor for Cost-Effective Oxide-TFT Inverters.
17. Rational Design of Phase-Engineered WS 2 /WSe 2 Heterostructures by Low-Temperature Plasma-Assisted Sulfurization and Selenization toward Enhanced HER Performance.
18. High-Performance Monolithic 3D Integrated Complementary Inverters Based on Monolayer n-MoS 2 and p-WSe 2 .
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