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This study implements a highly uniform 3D vertically stack resistive random‐access memory (VRRAM) with a four‐layer contact hole structure. The fabrication process of a four‐layer VRRAM is demonstrated, and its physical and electrical properties are thoroughly examined. X‐ray photoelectron spectroscopy and transmission electron microscopy are employed to analyze the chemical distribution and physical structure of the VRRAM device. Multilevel capability, reliable endurance (>104 cycles), and retention (104 s) are successfully obtained. Synaptic memory plasticity, such as spike time‐dependent plasticity, spike rate‐dependent plasticity, excitatory post‐synaptic current, paired‐pulse facilitation, and long‐term potentiation and depression is presented. Finally, the vector‐matrix multiplication (VMM) operation is conducted on a 4 × 12 VRRAM array, according to the low resistance state ratio. It is ascertained that the accuracy drop, which can occur due to VMM error, can be limited to a decrease of less than 0.44% point. Utilizing the high‐density, multilevel, and biological characteristics of VRRAM, it is possible to implement high‐performance neuromorphic systems that require densely integrated synaptic devices. [ABSTRACT FROM AUTHOR]

Memristors have diverse potential for improving data storage through linear memory control and synaptic operation in AI and neuromorphic computing. Prior research on optimizing memristors in next‐generation devices has generally indicated that emerging arrays and vertical structures can improve memory density, although special fabrication steps are required to realize improved operation. Until now, many obstructions, such as the sneak path current and forming processes from the initial device in array structure operation at the device level, have limited the development of array‐based memristor devices for further progressing circuits and integrated design. In this paper, memristor array studies are examined that have suggested solutions for sneak path current and forming operation problems at the device level. Ultimately, representative solutions are proposed to progress memristors into array structures by introducing the latest research on one diode‐one RRAM (1D1R), one selector‐one RRAM (1S1R), overshoot suppressed RRAM (OSRRAM), self‐rectifying cell (SRC), charge trap memory (CTM) and their applications. Additionally, essential details demonstrating the practical implementation of these devices in crossbar array memory are investigated. Finally, the advantages and perspectives of these array‐based memristor solutions are summarized. [ABSTRACT FROM AUTHOR]