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A novel sense-amplifier (SA) based flip-flop (FF) design is proposed to improve power and area efficiency for low-power applications. To reduce transistor count, a logic replacement technique is initially applied to the RS latch design. Following this, the discharge paths of both the sense-amplifier design and RS latch design are merged, effectively removing redundant transistors. This integration reduces layout area and addresses the additional power consumption from glitches observed in previous SAFF designs. These enhancements significantly decrease the clock-to-Q delay and average power consumption, with performance gains confirmed through post-layout simulations and chip measurements. [ABSTRACT FROM AUTHOR]